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| msp 34x5g multistandard sound processor family edition march 5, 2001 6251-480-3pd preliminar y d a t a sheet micr onas micronas
msp 34x5g preliminary data sheet 2 micronas contents page section title 5 1. introduction 6 1.1. features of the msp 34x5g family and differences to mspd 6 1.2. msp 34x5g version list 7 1.3. msp 34x5g versions and their application fields 8 2. functional description 9 2.1. architecture of the msp 34x5g family 9 2.2. sound if processing 9 2.2.1. analog sound if input 9 2.2.2. demodulator: standards and features 10 2.2.3. preprocessing of demodulator signals 10 2.2.4. automatic sound select 10 2.2.5. manual mode 12 2.3. preprocessing for scart and i 2 s input signals 12 2.4. source selection and output channel matrix 12 2.5. audio baseband processing 12 2.5.1. automatic volume correction (avc) 12 2.5.2. loudspeaker outputs 12 2.5.3. quasi-peak detector 13 2.6. scart signal routing 13 2.6.1. scart dsp in and scart out select 13 2.6.2. stand-by mode 13 2.7. i 2 s bus interface 14 2.8. adr bus interface 14 2.9. digital control i/o pins and status change indication 14 2.10. clock pll oscillator and crystal specifications 15 3. control interface 15 3.1. i 2 c bus interface 15 3.1.1. internal hardware error handling 16 3.1.2. description of control register 16 3.1.3. protocol description 17 3.1.4. proposals for general msp 34x5g i 2 c telegrams 17 3.1.4.1. symbols 17 3.1.4.2. write telegrams 17 3.1.4.3. read telegrams 17 3.1.4.4. examples 17 3.2. start-up sequence: power-up and i 2 c-controlling 17 3.3. msp 34x5g programming interface 17 3.3.1. user registers overview 20 3.3.2. description of user registers 21 3.3.2.1. standard select register 21 3.3.2.2. refresh of standard select register 21 3.3.2.3. standard result register 23 3.3.2.4. write registers on i 2 c subaddress 10 hex 25 3.3.2.5. read registers on i 2 c subaddress 11 hex 26 3.3.2.6. write registers on i 2 c subaddress 12 hex contents, continued page section title preliminary data sheet msp 34x5g micronas 3 36 3.3.2.7. read registers on i 2 c subaddress 13 hex 37 3.4. programming tips 37 3.5. examples of minimum initialization codes 37 3.5.1. b/g-fm (a2 or nicam) 37 3.5.2. btsc-stereo 37 3.5.3. btsc-sap with sap at loudspeaker channel 38 3.5.4. fm-stereo radio 38 3.5.5. automatic standard detection 38 3.5.6. software flow for interrupt driven status check 40 4. specifications 40 4.1. outline dimensions 42 4.2. pin connections and short descriptions 45 4.3. pin description 47 4.4. pin configurations 51 4.5. pin circuits 53 4.6. electrical characteristics 53 4.6.1. absolute maximum ratings 54 4.6.2. recommended operating conditions 54 4.6.2.1. general recommended operating conditions 54 4.6.2.2. analog input and output recommendations 55 4.6.2.3. recommendations for analog sound if input signal 56 4.6.2.4. crystal recommendations 58 4.6.3. characteristics 58 4.6.3.1. general characteristics 59 4.6.3.2. digital inputs, digital outputs 60 4.6.3.3. reset input and power-up 61 4.6.3.4. i 2 c bus characteristics 62 4.6.3.5. i 2 s-bus characteristics 64 4.6.3.6. analog baseband inputs and outputs, agndc 65 4.6.3.7. sound if input 65 4.6.3.8. power supply rejection 66 4.6.3.9. analog performance 69 4.6.3.10. sound standard dependent characteristics 73 5. appendix a: overview of tv sound standards 73 5.1. nicam 728 74 5.2. a2 systems 75 5.3. btsc-sound system 75 5.4. japanese fm stereo system (eia-j) 76 5.5. fm satellite sound 76 5.6. fm-stereo radio 77 6. appendix b: manual/compatibility mode 77 6.1. demodulator write and read registers for manual/compatibility mode 78 6.2. dsp write and read registers for manual/compatibility mode 79 6.3. manual/compatibility mode: description of demodulator write registers 79 6.3.1. automatic switching between nicam and analog sound msp 34x5g preliminary data sheet 4 micronas contents, continued page section title 79 6.3.1.1. function in automatic sound select mode 79 6.3.1.2. function in manual mode 81 6.3.2. a2 threshold 81 6.3.3. carrier-mute threshold 82 6.3.4. register ad_cv 83 6.3.5. register mode_reg 85 6.3.6. fir-parameter, registers fir1 and fir2 85 6.3.7. dco-registers 87 6.4. manual/compatibility mode: description of demodulator read registers 87 6.4.1. nicam mode control/additional data bits register 87 6.4.2. additional data bits register 87 6.4.3. cib bits register 88 6.4.4. nicam error rate register 88 6.4.5. pll_caps readback register 88 6.4.6. agc_gain readback register 88 6.4.7. automatic search function for fm-carrier detection in satellite mode 89 6.5. manual/compatibility mode: description of dsp write registers 89 6.5.1. additional channel matrix modes 89 6.5.2. volume modes of scart1 output 89 6.5.3. fm fixed deemphasis 89 6.5.4. fm adaptive deemphasis 89 6.5.5. nicam deemphasis 90 6.5.6. identification mode for a2 stereo systems 90 6.5.7. fm dc notch 90 6.6. manual/compatibility mode: description of dsp read registers 90 6.6.1. stereo detection register for a2 stereo systems 90 6.6.2. dc level register 91 6.7. demodulator source channels in manual mode 91 6.7.1. terrestric sound standards 91 6.7.2. sat sound standards 91 6.8. exclusions of audio baseband features 91 6.9. compatibility restrictions to msp 34x5d 93 7. appendix d: application information 93 7.1. phase relationship of analog outputs 94 7.2. application circuit 96 8. appendix e: msp 34x5g version history 96 9. data sheet history license notice: ?dolby pro logic? is a trademark of dolby laboratories. supply of this implementation of dolby technology does not convey a license nor imply a right under any patent, or any other in dustrial or intellec- tual property right of dolby laboratories, to use this implementation in any finished end-user or ready-to-use final product. c ompanies planning to use this implementation in products must obtain a license from dolby laboratories licensing corporation before designing such p roducts. preliminary data sheet msp 34x5g micronas 5 multistandard sound processor family release note: revision bars indicate significant changes to the previous edition. the hardware and software description in this document is valid for the msp 34x5g version b8 and following versions. 1. introduction the msp 34x5g family of single-chip multistandard sound processors covers the sound processing of all analog tv standards worldwide, as well as the nicam digital sound standards. the full tv sound processing, starting with analog sound if signal-in, down to pro- cessed analog af-out, is performed in a single chip. figure 1 ? 1 shows a simplified functional block diagram of the msp 34x5g. these tv sound processing ics include versions for processing the multichannel television sound (mts) signal conforming to the standard recommended by the broadcast television systems committee (btsc). the dbx noise reduction, or alternatively, micronas noise reduction (mnr) is performed alignment free. other processed standards are the japanese fm-fm multiplex standard (eia-j) and the fm-stereo-radio standard. current ics have to perform adjustment procedures in order to achieve good stereo separation for btsc and eia-j. the msp 34x5g has optimum stereo perfor- mance without any adjustments. all msp 34xxg versions are pin compatible to the msp 34xxd. only minor modifications are necessary to adapt a msp 34xxd controlling software to the msp 34xxg. the msp 34x5g further simplifies con- trolling software. standard selection requires a single i 2 c transmission only. note: the msp 34x5g version has reduced control registers and less functional pins. the remaining regis- ters are software-compatible to the msp 34x0g. the pinning is compatible to the msp 34x0g. the msp 34x5g has built-in automatic functions: the ic is able to detect the actual sound standard automat- ically (automatic standard detection). furthermore, pilot levels and identification signals can be evaluated internally with subsequent switching between mono/ stereo/bilingual; no i 2 c interaction is necessary (auto- matic sound selection). the msp 34x5g can handle very high fm deviations even in conjunction with nicam processing. this is especially important for the introduction of nicam in china. the ics are produced in submicron cmos technology. the msp 34x5g is available in the following packages: psdip64, psdip52, pmqfp44, plqfp64, and pqfp80. fig. 1?1: simplified functional block diagram of msp 34x5g source select loud- scart1 scart1 scart2 mono de- modulator speaker sound processing dac adc loud- dac adc sound if1 speaker i 2 s i 2 s1 i 2 s2 pre- processing prescale prescale scart dsp input select scart output select msp 34x5g preliminary data sheet 6 micronas 1.1. features of the msp 34x5g family and differences to mspd 1.2. msp 34x5g version list feature (new features not available for mspd are shaded gray.) 3405 3415 3425 3445 3455 3465 standard selection with single i 2 c transmission x x x x x x automatic standard detection of terrestrial tv standards x x x x x x automatic sound selection (mono/stereo/bilingual), new registers modus, status x x x x x x automatic carrier mute function x x x x x x interrupt output programmable (indicating status change) x x x x x x loudspeaker channel with volume, balance, bass, treble, loudness x x x x x x avc: automatic volume correction x x x x x x spatial effect for loudspeaker channel x x x x x x two stereo scart (line) inputs, one mono input; one stereo scart outputs x x x x x x complete scart in/out switching matrix x x x x x x tw o i 2 s inputs; one i 2 s output x x x x x x all analog mono sound carriers including am-secam l x x x x x x all analog fm-stereo a2 and satellite standards x x x all nicam standards xx simultaneous demodulation of (very) high-deviation fm-mono and nicam x x adaptive deemphasis for satellite (wegener-panda, acc. to astra specification) x x x x astra digital radio (adr) together with drp 3510a x x x demodulation of the btsc multiplex signal and the sap channel x x x alignment free digital dbx noise reduction for btsc stereo and sap x x alignment free digital micronas noise reduction (mnr) for btsc stereo and sap x btsc stereo separation (msp 3425/45g also eia-j) significantly better than spec. x x x sap and stereo detection for btsc system x x x korean fm-stereo a2 standard x x x x x alignment-free japanese standard eia-j x x x demodulation of the fm-radio multiplex signal x x x version status description msp 3405g available fm stereo (a2) version msp 3415g available nicam and fm stereo (a2) version msp 3425g available ntsc version (a2 korea, btsc with micronas noise reduction (mnr), japanese eia-j system) msp 3445g available ntsc version (a2 korea, btsc with dbx noise reduction, japanese eia-j system) msp 3455g available global stereo version (all sound standards) msp 3465g available global mono version (all sound standards) preliminary data sheet msp 34x5g micronas 7 1.3. msp 34x5g versions and their application fields ta b l e 1 ? 1 provides an overview of tv sound standards that can be processed by the msp 34x5g family. in addition, the msp 34x5g is able to handle the fm- radio standard. with the msp 34x5g, a complete multimedia receiver covering all tv sound standards together with terrestrial/cable and satellite radio sound can be built; even astra digital radio can be pro- cessed (with a drp 3510a coprocessor). fig. 1 ? 2: typical msp 34x5g application table 1 ? 1: tv stereo sound standards covered by the msp 34x5g ic family (details see appendix a) msp version tv- system position of sound carrier /mhz sound modulation color system broadcast e.g. in: 3405 3415 3455 b/g 5.5/5.7421875 fm-stereo (a2) pal germany 5.5/5.85 fm-mono/nicam pal scandinavia, spain l 6.5/5.85 am-mono/nicam secam-l france i 6.0/6.552 fm-mono/nicam pal uk, hong kong 3405 d/k 6.5/6.2578125 fm-stereo (a2, d/k1) secam-east slovak. rep. 6.5/6.7421875 fm-stereo (a2, d/k2) pal currently no broadcast 6.5/5.7421875 fm-stereo (a2, d/k3) secam-east poland 6.5/5.85 fm-mono/nicam (d/k, nicam) pal china, hungary 3405 satellite 6.5 7.02/7.2 7.38/7.56 etc. fm-mono fm-stereo astra digital radio (adr) with drp 3510a pa l europe sat. astra 3425, 3445 m/n 4.5/4.724212 fm-stereo (a2) ntsc korea 4.5 fm-fm (eia-j) ntsc japan 4.5 btsc-stereo + sap ntsc, pal usa, argentina fm-radio 10.7 fm-stereo radio usa, europe 3465 all standards as above, but mono demodulation only. 33 34 39 mhz 4.5 9 mhz 2 msp 34x5g 2 2 1 tuner saw filter vision demo- dulator composite video sound if mixer scart inputs mono scart1 scart2 loudspeaker scart output scart1 dolby pro logic processor dpl 351xa adr decoder drp 3510a i 2 s1 adr i 2 s2 msp 34x5g preliminary data sheet 8 micronas 2. functional description i 2 c stereo or b stereo or a fm/am fm/am prescale prescale nicam read register deemphasis: 50/75 s, j17 dbx/mnr standard demodulator (incl. carrier mute) decoded ? nicam ? a2 ? am ? btsc ? eia-j ? sat ? fm-radio and sound detection standards: deemphasis j17 stereo or a/b automatic sound select standard selection (0e hex ) (10 hex ) i 2 c read register d a scart1 channel matrix volume source select quasi-peak detector quasi-peak channel matrix loud- speaker channel matrix a d a d scart dsp input select scart output select scart1_l/r 0 1 3 4 5 2 6 (0d hex ) (08 hex ) (0c hex ) (0a hex )(07 hex ) (00 hex ) (29 hex ) (14 hex ) f ig. 2 ? 1: signal flow block diagram of the msp 34x5g (input and output names correspond to pin names). (13 hex ) (13 hex ) bass/ treble volume loud- ness spatial effects avc balance d a beeper (02 hex ) (03 hex ) (04 hex )(05 hex )(01 hex ) dacm_l dacm_r i 2 s channel matrix i 2 s interface (0b hex ) i 2 s interface i 2 s interface i 2 s1 i 2 s2 prescale prescale scart prescale sc1_in_l sc1_in_r sc2_in_l sc2_in_r mono_in ana_in1+ adr-bus interface agc i2s_da_in1 i2s_da_in2 (16 hex ) (12 hex ) i2s_da_out sc1_out_l sc1_out_r (19 hex ) (1a hex ) panda1 preliminary data sheet msp 34x5g micronas 9 2.1. architecture of the msp 34x5g family fig. 2 ? 1 on page 8 shows a simplified block diagram of the ic. the block diagram contains all features of the msp 3455g. other members of the msp 34x5g family do not have the complete set of features: the demodu- lator handles only a subset of the standards presented in the demodulator block; nicam processing is only possible in the msp 3415g and msp 3455g (see dashed block in fig. 2 ? 1). 2.2. sound if processing 2.2.1. analog sound if input the input pins ana_in1+ and ana_in ? offer the pos- sibility to connect sound if (sif) sources to the msp 34x5g. the analog-to-digital conversion of the sound if signal is done by an a/d-converter. an ana- log automatic gain circuit (agc) allows a wide range of input levels. the high-pass filter formed by the cou- pling capacitor at pin ana_in1+ (see section 7. ? appendix d: application information ? on page 93) is sufficient in most cases to suppress video compo- nents. some combinations of saw filters and sound if mixer ics, however, show large picture components on their outputs. in this case, further filtering is recom- mended. 2.2.2. demodulator: standards and features the msp 34x5g is able to demodulate all tv sound standards worldwide including the digital nicam sys- tem. depending on the msp 34x5g version, the fol- lowing demodulation modes can be performed: a2-systems: detection and demodulation of two sep- arate fm carriers (fm1 and fm2), demodulation and evaluation of the identification signal of carrier fm2. nicam-systems: demodulation and decoding of the nicam carrier, detection and demodulation of the ana- log (fm or am) carrier. for d/k-nicam, the fm carrier may have a maximum deviation of 384 khz. very high deviation fm-mono: detection and robust demodulation of one fm carrier with a maximum devi- ation of 540 khz. btsc-stereo: detection and fm demodulation of the aural carrier resulting in the mts/mpx signal. detec- tion and evaluation of the pilot carrier, am demodula- tion of the (l-r)-carrier and detection of the sap sub- carrier. processing of the dbx noise reduction or micronas noise reduction (mnr). btsc-mono + sap: detection and fm demodulation of the aural carrier resulting in the mts/mpx signal. detection and evaluation of the pilot carrier, detection and fm demodulation of the sap-subcarrier. process- ing of the dbx noise reduction or micronas noise reduction (mnr). japan stereo: detection and fm demodulation of the aural carrier resulting in the mpx signal. demodulation and evaluation of the identification signal and fm demodulation of the (l-r)-carrier. fm-satellite sound: demodulation of one or two fm carriers. processing of high-deviation mono or narrow bandwidth mono, stereo, or bilingual satellite sound according to the astra specification. fm-stereo-radio: detection and fm demodulation of the aural carrier resulting in the mpx signal. detection and evaluation of the pilot carrier and am demodula- tion of the (l-r)-carrier. the demodulator blocks of all msp 34x5g versions have identical user interfaces. even completely differ- ent systems like the btsc and nicam systems are controlled the same way. standards are selected by means of msp standard codes. automatic processes handle standard detection and identification without controller interaction. the key features of the msp 34x5g demodulator blocks are standard selection: the controlling of the demodula- tor is minimized: all parameters, such as tuning fre- quencies or filter bandwidth, are adjusted automati- cally by transmitting one single value to the standard select register. for all standards, spe- cific msp standard codes are defined. automatic standard detection: if the tv sound stan- dard is unknown, the msp 34x5g can automatically detect the actual standard, switch to that standard, and respond the actual msp standard code. automatic carrier mute: to prevent noise effects or fm identification problems in the absence of an fm carrier, the msp 34x5g offers a configurable carrier mute feature, which is activated automatically if the tv sound standard is selected by means of the stan- dard select register. if no fm carrier is detected at one of the two msp demodulator channels, the corre- sponding demodulator output is muted. this is indi- cated in the status register. msp 34x5g preliminary data sheet 10 micronas 2.2.3. preprocessing of demodulator signals the nicam signals must be processed by a deempha- sis filter and adjusted in level. the analog demodu- lated signals must be processed by a deemphasis fil- ter, adjusted in level, and dematrixed. the correct deemphasis filters are already selected by setting the standard in the standard select register. the level adjustment has to be done by means of the fm/ am and nicam prescale registers. the necessary dematrix function depends on the selected sound standard and the actual broadcasted sound mode (mono, stereo, or bilingual). it can be manually set by the fm matrix mode register or automatically by the automatic sound selection. 2.2.4. automatic sound select in the automatic sound select mode, the dematrix function is automatically selected based on the identifi- cation information in the status register. no i 2 c inter- action is necessary when the broadcasted sound mode changes (e.g. from mono to stereo). the demodulator supports the identification check by switching between mono-compatible standards (stan- dards that have the same fm-mono carrier) automati- cally and non-audible. if b/g-fm or b/g-nicam is selected, the msp will switch between these stan- dards. the same action is performed for the standards: d/k1-fm, d/k2-fm, d/k3-fm and d/k-nicam. switching is only done in the absence of any stereo or bilingual identification. if identification is found, the msp keeps the detected standard. in case of high bit-error rates, the msp 34x5g auto- matically falls back from digital nicam sound to ana- log fm or am mono. ta b l e 2 ? 1 summarizes all actions that take place when automatic sound select is switched on. to provide more flexibility, the automatic sound select block prepares four different source channels of demodulated sound (fig. 2 ? 2). by choosing one of the four demodulator channels, the preferred sound mode can be selected for each of the output channels (loud- speaker, headphone, etc.). this is done by means of the source select registers. the following source channels of demodulated sound are defined: ? ? fm/am ? channel: analog mono sound, stereo if available. in case of nicam, analog mono only (fm or am mono). ? ? stereo or a/b ? channel: analog or digital mono sound, stereo if available. in case of bilingual broad- cast, it contains both languages a (left) and b (right). ? ? stereo or a ? channel: analog or digital mono sound, stereo if available. in case of bilingual broad- cast, it contains language a (on left and right). ? ? stereo or b ? channel: analog or digital mono sound, stereo if available. in case of bilingual broad- cast, it contains language b (on left and right). fig. 2 ? 2 and table 2 ? 2 show the source channel assignment of the demodulated signals in case of automatic sound select mode for all sound standards. note: the analog primary input channel contains the signal of the mono fm/am carrier or the l+r signal of the mpx carrier. the secondary input channel con- tains the signal of the 2nd fm carrier, the l-r signal of the mpx carrier, or the sap signal. fig. 2 ? 2: source channel assignment of demodulated signals in automatic sound select mode 2.2.5. manual mode fig. 2 ? 3 shows the source channel assignment of demodulated signals in case of manual mode. if man- ual mode is required, more information can be found in section 6.7. ? demodulator source channels in manual mode ? on page 91. fig. 2 ? 3: source channel assignment of demodulated signals in manual mode source select fm/am stereo or a/b stereo or a stereo or b 0 1 3 4 primary fm/am prescale nicam prescale automatic sound select channel secondary channel nicam a nicam b ls ch. matrix output-ch. matrices must be set once to stereo. source select fm/am (stereo or a/b) 0 1 primary fm/am prescale nicam prescale fm-matrix channel secondary channel nicam a nicam b ls ch. matrix output-ch. matrices must be set according to the standard. nicam preliminary data sheet msp 34x5g micronas 11 table 2 ? 1: performed actions of the automatic sound selection selected tv sound standard performed actions b/g-fm, d/k-fm, m-korea, and m-japan evaluation of the identification signal and automatic switching to mono, stereo, or bilingual. preparing four demodulator source channels according to table 2 ? 2. b/g-nicam, l-nicam, i-nicam, d/k-nicam evaluation of nicam-c-bits and automatic switching to mono, stereo, or bilingual. preparing four demodulator source channels according to table 2 ? 2. in case of bad or no nicam reception, the msp switches automatically to fm/am mono and switches back to nicam if possible. a hysteresis prevents periodical switching. b/g-fm, b/g-nicam or d/k1-fm, d/k2-fm, d/k3-fm, and d/k-nicam automatic searching for stereo/bilingual-identification in case of mono transmission. automatic and non- audible changes between dual-fm and fm-nicam standards while listening to the basic fm-mono sound carrier. example: if starting with b/g-fm-stereo, there will be a periodical alternation to b/g-nicam in the absence of fm-stereo/bilingual or nicam-identification. once an identification is detected, the msp keeps the corresponding standard. btsc-stereo, fm radio evaluation of the pilot signal and automatic switching to mono or stereo. preparing four demodulator source channels according to table 2 ? 2. detection of the sap carrier. m-btsc-sap in the absence of sap, the msp switches to btsc-stereo if available. if sap is detected, the msp switches automatically to sap (see table 2 ? 2). table 2 ? 2: sound modes for the demodulator source channels with automatic sound select source channels in automatic sound select mode broadcasted sound standard selected msp standard code 3) broadcasted sound mode fm/am (source select: 0) stereo or a/b (source select: 1) stereo or a (source select: 3) stereo or b (source select: 4) m-korea b/g-fm d/k-fm m-japan 02 03, 08 1) 04, 05, 07, 0b 1) 30 mono mono mono mono mono stereo stereo stereo stereo stereo bilingual: languages a and b right = b left = a right = b ab b/g-nicam l-nicam i-nicam d/k-nicam d/k-nicam (with high deviation fm) 08, 03 2) 09 0a 0b, 04 2) , 05 2) 0c, 0d nicam not available or error rate too high analog mono analog mono analog mono analog mono mono analog mono nicam mono nicam mono nicam mono stereo analog mono nicam stereo nicam stereo nicam stereo bilingual: languages a and b analog mono left = nicam a right = nicam b nicam a nicam b btsc 20, 21 mono mono mono mono mono stereo stereo stereo stereo stereo 20 mono + sap mono mono mono mono stereo + sap stereo stereo stereo stereo 21 mono + sap left = mono right = sap left = mono right = sap mono sap stereo + sap left = mono right = sap left = mono right = sap mono sap fm radio 40 mono mono mono mono mono stereo stereo stereo stereo stereo 1) the automatic sound select process will automatically switch to the mono compatible analog standard. 2) the automatic sound select process will automatically switch to the mono compatible digital standard. 3) the msp standard codes are defined in table 3 ? 7 on page 20. msp 34x5g preliminary data sheet 12 micronas 2.3. preprocessing for scart and i 2 s input signals the scart and i 2 s inputs need only be adjusted in level by means of the scart and i 2 s prescale regis- ters. 2.4. source selection and output channel matrix the source selector makes it possible to distribute all source signals (one of the demodulator source chan- nels or scart) to the desired output channels (loud- speaker, etc.). all input and output signals can be pro- cessed simultaneously. each source channel is identified by a unique source address. for each output channel, the sound mode can be set to sound a, sound b, stereo, or mono by means of the output channel matrix. if automatic sound select is on, the output channel matrix can stay fixed to stereo (transparent) for demod- ulated signals. 2.5. audio baseband processing 2.5.1. automatic volume correction (avc) different sound sources (e.g. terrestrial channels, sat channels, or scart) fairly often do not have the same volume level. advertisements during movies usually have a higher volume level than the movie itself. this results in annoying volume changes. the avc solves this problem by equalizing the volume level. to prevent clipping, the avc ? s gain decreases quickly in dynamic boost conditions. to suppress oscillation effects, the gain increases rather slowly for low level inputs. the decay time is programmable by means of the avc register (see page 30). for input signals ranging from ? 24 dbr to 0 dbr, the avc maintains a fixed output level of ? 18 dbr. fig. 2 ? 4 shows the avc output level versus its input level. for prescale and volume registers set to 0 db, a level of 0 dbr corresponds to full scale input/output. this is ? scart input/output 0 dbr = 2.0 v rms ? loudspeaker output 0 dbr = 1.4 v rms fig. 2 ? 4: simplified avc characteristics 2.5.2. loudspeaker outputs the following baseband features are implemented in the loudspeaker output channels: bass/treble, loud- ness, balance, and volume. a square wave beeper can be added to the loudspeaker channel. 2.5.3. quasi-peak detector the quasi-peak readout register can be used to read out the quasi-peak level of any input source. the fea- ture is based on following filter time constants: attack time: 1.3 ms decay time: 37 ms ? 30 ? 24 ? 18 ? 12 ? 6 input level ? 18 ? 24 output level 0 [dbr] [dbr] preliminary data sheet msp 34x5g micronas 13 2.6. scart signal routing 2.6.1. scart dsp in and scart out select the scart dsp input select and scart output select blocks include full matrix switching facilities. to design a tv set with two pairs of scart-inputs and one pair of scart-outputs, no external switching hardware is required. the switches are controlled by the acb user register (see page 34). 2.6.2. stand-by mode if the msp 34x5g is switched off by first pulling standbyq low and then (after >1 s delay) switching off dvsup and avsup, but keeping ahvsup ( ? stand-by ? -mode ), the scart switches maintain their position and function. this allows the copying from selected scart-inputs to scart-outputs in the tv set ? s stand-by mode. in case of power on or starting from stand-by (switch- ing on the dvsup and avsup, resetq going high 2 ms later), all internal registers except the acb regis- ter (page 34) are reset to the default configuration (see ta b l e 3 ? 5 on page 18). the reset position of the acb register becomes active after the first i 2 c transmission into the baseband processing part. by transmitting the acb register first, the reset state can be redefined. 2.7. i 2 s bus interface the msp 34x5g has a synchronous master/slave input/output interface running on 32 khz. the interface accepts two formats: 1. i 2 s_ws changes at the word boundary 2. i 2 s_ws changes one i 2 s-clock period before the word boundaries. all i 2 s options are set by means of the modus and the i2s_config registers. the i 2 s bus interface consists of five pins: ? i 2 s _ d a _ i n 1 , i 2 s _ d a _ i n 2 : i 2 s serial data input: 16, 18....32 bits per sample ? i 2 s _ da _ o u t : i 2 s serial data output: 16, 18...32 bits per sample ? i2s _cl : i 2 s serial clock ? i 2 s _ w s : i 2 s word strobe signal defines the left and right sample if the msp 34x5g serves as the master on the i 2 s interface, the clock and word strobe lines are driven by the ic. in this mode, only 16 or 32 bits per sample can be selected. in slave mode, these lines are input to the ic and the msp clock is synchronized to 576 times the i2s_ws rate (32 khz). nicam operation is not possi- ble in slave mode. an i 2 s timing diagram is shown in fig. 4 ? 28 on page 63. msp 34x5g preliminary data sheet 14 micronas 2.8. adr bus interface for the astra digital radio system (adr), the msp 3405g, msp 3415g, and msp 3455g performs preprocessing such as carrier selection and filtering. via the 3-line adr-bus, the resulting signals are trans- ferred to the drp 3510a coprocessor, where the source decoding is performed. to be prepared for an upgrade to adr with an additional drp board, the fol- lowing lines of msp 34x5g should be provided on a feature connector: ? i2s_da_in1 or i2s_da_in2 ? i2s_da_out ? i2s_ws ? i2s_cl ? adr_cl, adr_ws, adr_da for more details, please refer to the drp 3510a data sheet. 2.9. digital control i/o pins and status change indication the static level of the digital input/output pins d_ctr_i/o_0/1 is switchable between high and low via the i 2 c-bus by means of the acb register (see page 34). this enables the controlling of external hardware switches or other devices via i 2 c-bus. the digital input/output pins can be set to high imped- ance by means of the modus register (see page 23). in this mode, the pins can be used as input. the cur- rent state can be read out of the status register (see page 25). optionally, the pin d_ctr_i/o_1 can be used as an interrupt request signal to the controller, indicating any changes in the read register status. this makes poll- ing unnecessary; i 2 c-bus interactions are reduced to a minimum (see status register on page 25 and modus register on page 23). 2.10. clock pll oscillator and crystal specifications the msp 34x5g derives all internal system clocks from the 18.432 mhz oscillator. in nicam or in i 2 s- slave mode, the clock is phase-locked to the corre- sponding source. therefore, it is not possible to use nicam and i 2 s-slave mode at the same time. for proper performance, the msp clock oscillator requires a 18.432-mhz crystal. note, that for the phase-locked mode (nicam, i 2 s slave), crystals with tighter tolerance are required. preliminary data sheet msp 34x5g micronas 15 3. control interface 3.1. i 2 c bus interface the msp 34x5g is controlled via the i 2 c bus slave interface. the ic is selected by transmitting one of the msp 34x5g device addresses. in order to allow up to three msp ics to be connected to a single bus, an address select pin (adr_sel) has been implemented. with adr_sel pulled to high, low, or left open, the msp 34x5g responds to different device addresses. a device address pair is defined as a write address and a read address (see table 3 ? 1). writing is done by sending the write device address, followed by the subaddress byte, two address bytes, and two data bytes. reading is done by sending the write device address, followed by the subaddress byte and two address bytes. without sending a stop condition, reading of the addressed data is completed by sending the device read address and reading two bytes of data. refer to section 3.1.3. for the i 2 c bus protocol and to section 3.4. ? programming tips ? on page 37 for pro- posals of msp 34x5g i 2 c telegrams. see table 3 ? 2 for a list of available subaddresses. besides the possibility of hardware reset, the msp can also be reset by means of the reset bit in the con- trol register by the controller via i 2 c bus. due to the architecture of the msp 34x5g, the ic can- not react immediately to an i 2 c request. the typical response time is about 0.3 ms. if the msp cannot accept another byte of data (e.g. while servicing an internal interrupt), it holds the clock line i2c_cl low to force the transmitter into a wait state. the i 2 c bus master must read back the clock line to detect when the msp is ready to receive the next i 2 c transmission. the positions within a transmission where this may happen are indicated by ? wait ? in section 3.1.3. the maximum wait period of the msp during normal opera- tion mode is less than 1 ms. 3.1.1. internal hardware error handling in case of any hardware problems (e.g. interruption of the power supply of the msp), the msp ? s wait period is extended to 1.8 ms. after this time period elapses, the msp releases data and clock lines. indication and solving the error status: to indicate the error status, the remaining acknowl- edge bits of the actual i 2 c-protocol will be left high. additionally, bit[14] of control is set to one. the msp can then be reset via the i 2 c bus by transmitting the reset condition to control. indication of reset: any reset, even caused by an unstable reset line etc., is indicated in bit[15] of control. a general timing diagram of the i 2 c bus is shown in fig. 4 ? 27 on page 61. table 3 ? 1: i 2 c bus device addresses adr_sel low (connected to dvss) high (connected to dvsup) left open mode write read write read write read msp device address 80 hex 81 hex 84 hex 85 hex 88 hex 89 hex table 3 ? 2: i 2 c bus subaddresses name binary value hex value mode function control 0000 0000 00 read/write write: software reset of msp (see table 3 ? 3) read: hardware error status of msp wr_dem 0001 0000 10 write write address demodulator rd_dem 0001 0001 11 write read address demodulator wr_dsp 0001 0010 12 write write address dsp rd_dsp 0001 0011 13 write read address dsp msp 34x5g preliminary data sheet 16 micronas 3.1.2. description of control register 3.1.3. protocol description write to dsp or demodulator read from dsp or demodulator write to control register read from control register note: s = i 2 c-bus start condition from master p = i 2 c-bus stop condition from master ack = acknowledge-bit: low on i2c_da from slave (= msp, light gray) or master (= controller, dark gray) nak = not acknowledge-bit: high on i2c_da from master (dark gray) to indicate ? end of read ? or from msp indicating internal error state wait = i 2 c-clock line is held low, while the msp is processing the i 2 c command. this waiting time is max. 1 ms table 3 ? 3: control as a write register name subaddress bit[15] (msb) bits[14:0] control 00 hex 1 : reset 0 : normal 0 table 3 ? 4: control as a read register name subaddress bit bit control 00 hex reset status after last reading of control: 0 : no reset occured 1 : reset occured internal hardware status: 0 : no error occured 1 : internal error occured not of interest reading of control will reset the bits[15,14] of control. after power-on, bit[15] of control will be set; it must be read once to be reset. swrite device address wait ack sub-addr ack addr-byte high ack addr-byte low ack data-byte high ack data-byte low ack p swrite device address wait ack sub-addr ack addr-byte high ack addr-byte low ack s read device address wait ack data-byte- high ack data-byte low nak p swrite device address wait ack sub-addr ack data-byte high ack data-byte low ack p swrite device address wait ack 00hex ack s read device address wait ack data-byte- high ack data-byte low nak p preliminary data sheet msp 34x5g micronas 17 fig. 3 ? 1: i 2 c bus protocol (msb first; data must be stable while clock is high) 3.1.4. proposals for general msp 34x5g i 2 c telegrams 3.1.4.1. symbols daw write device address (80 hex , 84 hex or 88 hex ) dar read device address (81 hex , 85 hex or 89 hex ) < start condition > stop condition aa address byte dd data byte 3.1.4.2. write telegrams msp 34x5g preliminary data sheet 18 micronas . table 3 ? 5: list of msp 34x5g write registers write register address (hex) bits description and adjustable range reset see page i 2 c sub-address = 10 hex ; registers are not readable standard select 00 20 [15:0] initial programming of the demodulator 00 00 21 modus 00 30 [15:0] demodulator, automatic and i 2 s options 00 00 23 i 2 s configuration 00 40 [15:0] configuration of i 2 s options 00 00 24 i 2 c sub-address = 12 hex ; registers are all readable by using i 2 c sub-address = 13 hex volume loudspeaker channel 00 00 [15:8] [+12 db ... ? 114 db, mute] mute 29 volume / mode loudspeaker channel [7:0] 1/8 db steps, reduce volume / tone control / compromise / dynamic 00 hex balance loudspeaker channel [l/r] 00 01 [15:8] [0..100 / 100 % and 100 /0..100 %] [ ? 127..0 / 0 and 0 / ? 127..0 db] 100 %/100 % 30 balance mode loudspeaker [7:0] [linear /logarithmic mode] linear mode bass loudspeaker channel 00 02 [15:8] [ + 20 db ... ? 12 db] 0 db 31 treble loudspeaker channel 00 03 [15:8] [ + 15 db ... ? 12 db] 0 db 31 loudness loudspeaker channel 00 04 [15:8] [0 db ... + 17 db] 0 db 32 loudness filter characteristic [7:0] [normal, super_bass] normal spatial effect strength loudspeaker ch. 00 05 [15:8] [ ? 100 %...off... + 100 %] off 33 spatial effect mode/customize [7:0] [sbe, sbe+pse] sbe+pse volume scart1 output channel 00 07 [15:8] [ + 12 db ... ? 114 db, mute] mute 34 loudspeaker source select 00 08 [15:8] [fm/am, nicam, scart, i 2 s1, i 2 s2] fm/am 28 loudspeaker channel matrix [7:0] [sounda, soundb, stereo, mono...] sounda 28 scart1 source select 00 0a [15:8] [fm/am, nicam, scart, i 2 s1, i 2 s2] fm/am 28 scart1 channel matrix [7:0] [sounda, soundb, stereo, mono...] sounda 28 i 2 s source select 00 0b [15:8] [fm/am, nicam, scart, i 2 s1, i 2 s2] fm/am 28 i 2 s channel matrix [7:0] [sounda, soundb, stereo, mono...] sounda 28 quasi-peak detector source select 00 0c [15:8] [fm/am, nicam, scart, i 2 s1, i 2 s2] fm/am 28 quasi-peak detector matrix [7:0] [sounda, soundb, stereo, mono...] sounda 28 prescale scart input 00 0d [15:8] [00 hex ... 7f hex ]00 hex 27 prescale fm/am 00 0e [15:8] [00 hex ... 7f hex ]00 hex 26 fm matrix [7:0] [no_mat, gsterero, kstereo] no_mat 27 prescale nicam 00 10 [15:8] [00 hex ... 7f hex ] (msp 3410g, msp 3450g only) 00 hex 27 prescale i 2 s2 00 12 [15:8] [00 hex ... 7f hex ]10 hex 27 acb : scart switches a. d_ctr_i/o 00 13 [15:0] bits[15:0] 00 hex 34 beeper 00 14 [15:0] [00 hex ... 7f hex ]/[00 hex ... 7f hex ]0/035 prescale i 2 s1 00 16 [15:8] [00 hex ... 7f hex ]10 hex 27 automatic volume correction 00 29 [15:8] [off, on, decay time] off 30 preliminary data sheet msp 34x5g micronas 19 table 3 ? 6: list of msp 34x5g read registers read register address (hex) bits description and adjustable range see page i 2 c sub-address = 11 hex ; registers are not writable standard result 00 7e [15:0] result of automatic standard detection (see table 3 ? 8) (msp 3415g, msp 3440g, msp 3455g only) 25 status 02 00 [15:0] monitoring of internal settings e.g. stereo, mono, mute etc. 25 i 2 c sub-address = 13 hex ; registers are not writable quasi-peak readout left 00 19 [15:0] [00 hex ... 7fff hex ] 16 bit two ? s complement 36 quasi-peak readout right 00 1a [15:0] [00 hex ... 7fff hex ] 16 bit two ? s complement 36 msp hardware version code 00 1e [15:8] [00 hex ... ff hex ]36 msp major revision code [7:0] [00 hex ... ff hex ]36 msp product code 00 1f [15:8] [00 hex ... ff hex ]36 msp rom version code [7:0] [00 hex ... ff hex ]36 msp 34x5g preliminary data sheet 20 micronas 3.3.2. description of user registers table 3 ? 7: standard codes for standard select register msp standard code (data in hex) tv sound standard sound carrier frequencies in mhz msp 34x5g version automatic standard detection 00 01 starts automatic standard detection and sets detected standard all standard selection 00 02 m-dual fm-stereo 4.5/4.724212 3405, -15, -25, -45, -55 00 03 b/g-dual fm-stereo 1) 5.5/5.7421875 3405, -15, -55 00 04 d/k1-dual fm-stereo 2) 6.5/6.2578125 00 05 d/k2-dual fm-stereo 2) 6.5/6.7421875 00 06 d/k -fm-mono with hdev3 3) , not detectable by automatic standard detection, for china hdev3 3) sat-mono (i.e. eutelsat, s. table 6 ? 18) 6.5 00 07 d/k3-dual fm-stereo 6.5/5.7421875 00 08 b/g-nicam-fm 1) 5.5/5.85 3415, -55 00 09 l-nicam-am 6.5/5.85 00 0a i-nicam-fm 6.0/6.552 00 0b d/k-nicam-fm 2) 6.5/5.85 00 0c d/k-nicam-fm with hdev2 4) , not detectable by automatic standard detection, for china 6.5/5.85 00 0d d/k-nicam-fm with hdev3 3) , not detectable by automatic standard detection, for china 6.5/5.85 00 20 btsc-stereo 4.5 3425, -45, -55 00 21 btsc-mono + sap 00 30 m-eia-j japan stereo 4.5 3425, -45, -55 00 40 fm-stereo radio with 75 s deemphasis 10.7 3425, -45, -55 00 50 sat-mono (see table 6 ? 18) 6.5 3405, -15, -55 00 51 sat-stereo (see table 6 ? 18) 7.02/7.20 00 60 sat adr (astra digital radio) 6.12 1) in case of automatic sound select, the b/g-codes 3 hex and 8 hex are equivalent. 2) in case of automatic sound select, the d/k-codes 4 hex , 5 hex , 7 hex , and b hex are equivalent. 3) hdev3: max. fm deviation must not exceed 540 khz 4) hdev2: max. fm deviation must not exceed 360 khz preliminary data sheet msp 34x5g micronas 21 3.3.2.1. standard select register the tv sound standard of the msp 34x5g demodula- tor is determined by the standard select register. there are two ways to use the standard select register: ? setting up the demodulator for a tv sound standard by sending the corresponding standard code with a single i 2 c bus transmission. ? starting the automatic standard detection for ter- restrial tv standards. this is the most comfortable way to set up the demodulator (not for msp 3435g). within 0.5 s the detection and setup of the actual tv sound standard is performed. the detected stan- dard can be read out of the standard result register by the control processor. this feature is rec- ommended for the primary setup of a tv set. out- puts should be muted during automatic standard detection. the standard codes are listed in table 3 ? 7. selecting a tv sound standard via the standard select register initializes the demodulator. this includes: agc-settings and carrier mute, tuning fre- quencies, fir-filter settings, demodulation mode (fm, am, nicam), deemphasis and identification mode. tv stereo sound standards that are unavailable for a specific msp version are processed in analog mono sound of the standard. in that case, stereo or bilingual processing will not be possible. for a complete setup of the tv sound processing from analog if input to the source selection, the transmis- sions as shown in section 3.5. are necessary. for reasons of software compatibility to the msp 34xxd, a manual/compatibility mode is available. a detailed description of this mode can be found on page 77. 3.3.2.2. refresh of standard select register a general refresh of the standard select register is not allowed. however, the following method enables watching the msp 34x5g ? alive ? status and detection of accidental resets (only versions b6 and later): ? after power-on, bit[15] of control will be set; it must be read once to enable the reset-detection feature. ? reading of the control register and checking the reset indicator bit[15] . ? if bit[15] is ? 0 ? , any refresh of the standard select register is not allowed. ? if bit[15] is ? 1 ? , indicating a reset, a refresh of the standard select register and all other mspg registers is required. 3.3.2.3. standard result register if automatic standard detection is selected in the standard select register, status and result of the automatic standard detection process can be read out of the standard result register. the possible results are based on the mentioned standard code and are listed in table 3 ? 8. in cases where no sound standard has been detected (no standard present, too much noise, strong interfer- ers, etc.) the standard result register contains 00 00 hex . in that case, the controller has to start further actions (for example set the standard according to a preference list or by manual input). as long as the standard result register contains a value greater than 07 ff hex , the automatic standard detection is still active. during this period, the modus and standard select register must not be written. the status register will be updated when the auto- matic standard detection has finished. if a present sound standard is unavailable for a specific msp-version, it detects and switches to the analog mono sound of this standard. example: the msps 3425g and 3445g will detect a b/g-nicam signal as standard 3 and will switch to the analog fm- mono sound. msp 34x5g preliminary data sheet 22 micronas table 3 ? 8: results of the automatic standard detection broadcasted sound standard standard result register read 007e hex automatic standard detection could not find a sound standard 0000 hex b/g-fm 0003 hex b/g-nicam 0008 hex i000a hex fm-radio 0040 hex m-korea m-japan m-btsc 0002 hex (if modus[14,13]=00) 0020 hex (if modus[14,13]=01) 0030 hex (if modus[14,13]=10) l-am d/k1 d/k2 d/k3 0009 hex (if modus[12]=0) 0004 hex (if modus[12]=1) l-nicam d/k-nicam 0009 hex (if modus[12]=0) 000b hex (if modus[12]=1) automatic standard detection still active >07ff hex preliminary data sheet msp 34x5g micronas 23 3.3.2.4. write registers on i 2 c subaddress 10 hex table 3 ? 9: write registers on i 2 c subaddress 10 hex register address function name 00 20 hex standard selection register defines tv-sound or fm-radio standard bit[15:0] 00 01 hex start automatic standard detection 00 02 hex msp standard codes (see table 3 ? 7) ... 00 60 hex standard_sel 00 30 hex modus register preference in automatic standard detection: bit[15] 0 undefined, must be 0 bit[14:13] detected 4.5 mhz carrier is interpreted as: 1) 0 standard m (korea) 1 standard m (btsc) 2 standard m (japan) 3 chroma carrier (m/n standards are ignored) bit[12] detected 6.5 mhz carrier is interpreted as: 1) 0 standard l (secam) 1 standard d/k1, d/k2, d/k3, or d/k nicam general msp 34x5g options bit[11:8] 0 undefined, must be 0 bit[7] 0/1 active/tristate state of audio clock output pin aud_cl_out bit[6] i 2 s word strobe alignment 0 ws changes at data word boundary 1 ws changes one clock cycle in advance bit[5] 0/1 master/slave mode of i 2 s interface (must be set to 0 (= master) in case of nicam mode) bit[4] 0/1 active/tristate state of i 2 s output pins bit[3] state of digital output pins d_ctr_i/o_0 and _1 0 active: d_ctr_i/o_0 and _1 are output pins (can be set by means of the acb register. see also: modus[1]) 1 tristate: d_ctr_i/o_0 and _1 are input pins (level can be read out of status[4,3]) bit[2] 0 undefined, must be 0 bit[1] 0/1 disable/enable status change indication by means of the digital i/o pin d_ctr_i/o_1 necessary condition: modus[3] = 0 (active) bit[0] 0/1off/on: automatic sound select modus 1) valid at the next start of automatic standard detection. msp 34x5g preliminary data sheet 24 micronas 00 40 hex i 2 s configuration register bit[15:1] 0 not used, must be set to ? 0 ? bit[0] i2s_cl frequency and i 2 s data sample length for master mode 0 2 x 16 bit (1.024 mhz) 1 2 x 32 bit (2.048 mhz)) i2s_config table 3 ? 9: write registers on i 2 c subaddress 10 hex , continued register address function name preliminary data sheet msp 34x5g micronas 25 3.3.2.5. read registers on i 2 c subaddress 11 hex table 3 ? 10: read registers on i 2 c subaddress 11 hex register address function name 00 7e hex standard result register readback of the detected tv sound or fm-radio standard bit[15:0] 00 00 hex automatic standard detection could not find a sound standard 00 02 hex msp standard codes (see table 3 ? 8) ... 00 40 hex >07 ff hex automatic standard detection still active standard_res 02 00 hex status register contains all user relevant internal information about the status of the msp bit[15:10] undefined bit[8] 0/1 ? 1 ? indicates bilingual sound mode or sap present (internally evaluated from received analog or digital iden- tification signals) bit[7] 0/1 ? 1 ? indicates independent mono sound (only for nicam) bit[6] 0/1 mono/stereo indication (internally evaluated from received analog or digital iden- tification signals) bit[5,9] 00 analog sound standard (fm or am) active 01 this pattern will not occur 10 digital sound (nicam) available 11 bad reception condition of digital sound (nicam) due to: a. high error rate b. unimplemented sound code c. data transmission only bit[4] 0/1 low/high level of digital i/o pin d_ctr_i/o_1 bit[3] 0/1 low/high level of digital i/o pin d_ctr_i/o_0 bit[2] 0 detected secondary carrier (2nd a2 or sap sub-carrier) 1 no secondary carrier detected bit[1] 0 detected primary carrier (mono or mpx carrier) 1 no primary carrier detected bit[0] undefined if status change indication is activated by means of modus[1]: each change in the status register sets the digital i/o pin d_ctr_i/o_1 to high level. reading the status register resets d_ctr_i/o_1. status msp 34x5g preliminary data sheet 26 micronas 3.3.2.6. write registers on i 2 c subaddress 12 hex table 3 ? 11: write registers on i 2 c subaddress 12 hex register address function name preprocessing 00 0e hex fm/am prescale bit[15:8] 00 hex defines the input prescale gain for the demodulated ... fm or am signal 7f hex 00 hex off (reset condition) for all fm modes except satellite fm and am-mode, the combinations of pres- cale value and fm deviation listed below lead to internal full scale. fm mode bit[15:8] 7f hex 28 khz fm deviation 48 hex 50 khz fm deviation 30 hex 75 khz fm deviation 24 hex 100 khz fm deviation 18 hex 150 khz fm deviation 13 hex 180 khz fm deviation (limit) fm high deviation mode (hdev2, msp standard code = c hex ) bit[15:8] 30 hex 150 khz fm deviation 14 hex 360 khz fm deviation (limit) fm very high deviation mode (hdev3, msp standard code = 6 and d hex ) bit[15:8] 20 hex 450 khz fm deviation 1a hex 540 khz fm deviation (limit) satellite fm with adaptive deemphasis bit[15:8] 10 hex recommendation am mode (msp standard code = 9) bit[15:8] 7c hex recommendation for sif input levels from 0.1 v pp to 0.8 v pp (due to the agc being switched on, the am-output level remains stable and independent of the actual sif-level in the mentioned input range) pre_fm preliminary data sheet msp 34x5g micronas 27 (continued) 00 0e hex fm matrix modes defines the dematrix function for the demodulated fm signal bit[7:0] 00 hex no matrix (used for bilingual and unmatrixed stereo sound) 01 hex german stereo (standard b/g) 02 hex korean stereo (also used for btsc, eia-j and fm radio) 03 hex sound a mono (left and right channel contain the mono sound of the fm/am mono carrier) 04 hex sound b mono in case of automatic sound select = on , the fm matrix mode is set automati- cally. writing to the fm/am prescale register (00 0e hex high part) is still allowed. in order not to disturb the automatic process, the low part of any i 2 c transmis- sion to this register is ignored. therefore, any fm-matrix readback values may differ from data written previously. in case of automatic sound select = off , the fm matrix mode must be set as shown in table 6 ? 17 of appendix b. to enable a forced mono mode for all analog stereo systems by overriding the internal pilot or identification evaluation, the following steps must be transmitted: 1. modus with bit[0] = 0 (automatic sound select off) 2. fm presc./matrix with fm matrix = sound a mono (sap: sound b mono) 3. select fm/am source channel, with channel matrix set to ? stereo ? (transparent) fm_matrix 00 10 hex nicam prescale defines the input prescale value for the digital nicam signal bit[15:8] 00 hex ... 7f hex prescale gain examples: 00 hex off 20 hex 0db gain 5a hex 9 db gain (recommendation) 7f hex + 12 db gain (maximum gain) pre_nicam 00 16 hex 00 12 hex i2s1 prescale i2s2 prescale defines the input prescale value for digital i 2 s input signals bit[15:8] 00 hex ... 7f hex prescale gain examples: 00 hex off 10 hex 0 db gain (recommendation, reset condition) 7f hex + 18 db gain (maximum gain) pre_i2s1 pre_i2s2 00 0d hex scart input prescale defines the input prescale value for the analog scart input signal bit[15:8] 00 hex ... 7f hex prescale gain examples: 00 hex off (reset condition) 19 hex 0db gain (2 v rms input leads to digital full scale) 7f hex + 14 db gain (400 mv rms input leads to digital full scale) pre_scart table 3 ? 11: write registers on i 2 c subaddress 12 hex , continued register address function name msp 34x5g preliminary data sheet 28 micronas source select and output channel matrix 00 08 hex 00 0a hex 00 0b hex 00 0c hex source for: loudspeaker output scart1 da output i 2 s output quasi-peak detector bit[15:8] 0 ? fm/am ? : demodulated fm or am mono signal 1 ? stereo or a/b ? : demodulator stereo or a/b signal (in manual mode, this source is identical to the nicam source in the msp 3410d) 3 ? stereo or a ? : demodulator stereo sound or language a (only defined for automatic sound select) 4 ? stereo or b ? : demodulator stereo sound or language b (only defined for automatic sound select) 2 scart input 5i 2 s1 input 6i 2 s2 input for demodulator sources, see table 2 ? 2. src_main src_scart1 src_i2s src_qpeak 00 08 hex 00 0a hex 00 0b hex 00 0c hex matrix mode for: loudspeaker output scart1 da output i 2 s output quasi-peak detector bit[7:0] 00 hex sound a mono (or left mono) (reset condition) 10 hex sound b mono (or right mono) 20 hex stereo (transparent mode) 30 hex mono (sum of left and right inputs divided by 2) special modes are available (see section 6.5.1. on page 89) in automatic sound select mode, the demodulator source channels are set according to table 2 ? 2. therefore, the matrix modes of the corresponding out- put channels should be set to ? stereo ? (transparent). mat_main mat_scart1 mat_i2s mat_qpeak table 3 ? 11: write registers on i 2 c subaddress 12 hex , continued register address function name preliminary data sheet msp 34x5g micronas 29 loudspeaker processing 00 00 hex volume loudspeaker bit[15:8] volume table with 1 db step size 7f hex + 12 db (maximum volume) 7e hex + 11 db ... 74 hex + 1db 73 hex 0db 72 hex ? 1db ... 02 hex ? 113 db 01 hex ? 114 db 00 hex mute (reset condition) ff hex fast mute (needs about 75 ms until the signal is com- pletely ramped down) bit[7:5] higher resolution volume table 0 + 0db 1 + 0.125 db increase in addition to the volume table ... 7 + 0.875 db increase in addition to the volume table bit[4] 0 must be set to 0 bit[3:0] clipping mode 0 reduce volume 1 reduce tone control 2 compromise 3 dynamic with large scale input signals, positive volume settings may lead to signal clip- ping. the msp 34x5g loudspeaker and headphone volume function is divided into a digital and an analog section. with fast mute, volume is reduced to mute posi- tion by digital volume only. analog volume is not changed. this reduces any audible dc plops. to turn volume on again, the volume step that has been used before fast mute was activated must be transmitted. if the clipping mode is set to ? reduce volume ? , the following rule is used: to prevent severe clipping effects with bass, treble, or equalizer boosts, the inter- nal volume is automatically limited to a level where, in combination with either bass, treble, or equalizer setting, the amplification does not exceed 12 db. if the clipping mode is ? reduce tone control ? , the bass or treble value is reduced if amplification exceeds 12 db. if the equalizer is switched on, the gain of those bands is reduced, where amplification together with volume exceeds 12 db. if the clipping mode is ? compromise ? , the bass or treble value and volume are reduced half and half if amplification exceeds 12 db. if the equalizer is switched on, the gain of those bands is reduced half and half, where amplification together with volume exceeds 12 db. if the clipping mode is ? dynamic ? , volume is reduced automatically if the signal amplitudes would exceed ? 2 dbfs within the ic. vol_main table 3 ? 11: write registers on i 2 c subaddress 12 hex , continued register address function name msp 34x5g preliminary data sheet 30 micronas 00 29 hex automatic volume correction (avc) loudspeaker channel bit[15:12] 00 hex avc off (and reset internal variables) 08 hex avc on bit[11:8] 08 hex 8 sec decay time 04 hex 4 sec decay time (recommended) 02 hex 2 sec decay time 01 hex 20 ms decay time (should be used for approx. 100 ms after channel change) note: avc should not be used in any dolby prologic mode (with dpl35xx), except in panorama or 3d-panorama mode, when only the loudspeaker output is active. avc avc_decay 00 01 hex balance loudspeaker channel bit[15:8] linear mode 7f hex left muted, right 100% 7e hex left 0.8%, right 100% ... 01 hex left 99.2%, right 100% 00 hex left 100%, right 100% ff hex left 100%, right 99.2% ... 82 hex left 100%, right 0.8% 81 hex left 100%, right muted bit[15:8] logarithmic mode 7f hex left ? 127 db, right 0 db 7e hex left ? 126 db, right 0 db ... 01 hex left ? 1 db, right 0 db 00 hex left 0 db, right 0 db ff hex left 0 db, right ? 1db ... 81 hex left 0 db, right ? 127 db 80 hex left 0 db, right ? 128 db bit[7:0] balance mode 00 hex linear 01 hex logarithmic positive balance settings reduce the left channel without affecting the right channel; negative settings reduce the right channel leaving the left channel unaffected. bal_main table 3 ? 11: write registers on i 2 c subaddress 12 hex , continued register address function name preliminary data sheet msp 34x5g micronas 31 00 02 hex bass loudspeaker channel bit[15:8] extended range 7f hex + 20 db 78 hex + 18 db 70 hex + 16 db 68 hex + 14 db normal range 60 hex + 12 db 58 hex + 11 db ... 08 hex + 1db 00 hex 0db f8 hex ? 1db ... a8 hex ? 11 db a0 hex ? 12 db higher resolution is possible: an lsb step in the normal range results in a gain step of about 1/8 db, in the extended range about 1/4 db. with positive bass settings, internal clipping may occur even with overall volume less than 0 db. this will lead to a clipped output signal. therefore, it is not rec- ommended to set bass to a value that, in conjunction with volume, would result in an overall positive gain. bass_main 00 03 hex treble loudspeaker channel bit[15:8] 78 hex + 15 db 70 hex + 14 db ... 08 hex + 1db 00 hex 0db f8 hex ? 1db ... a8 hex ? 11 db a0 hex ? 12 db higher resolution is possible: an lsb step results in a gain step of about 1/8 db. with positive treble settings, internal clipping may occur even with overall vol- ume less than 0 db. this will lead to a clipped output signal. therefore, it is not recommended to set treble to a value that, in conjunction with volume, would result in an overall positive gain. treb_main table 3 ? 11: write registers on i 2 c subaddress 12 hex , continued register address function name msp 34x5g preliminary data sheet 32 micronas 00 04 hex loudness loudspeaker channel bit[15:8] loudness gain 44 hex + 17 db 40 hex + 16 db ... 04 hex + 1db 03 hex + 0.75 db 02 hex + 0.5 db 01 hex + 0.25 db 00 hex 0db bit[7:0] loudness mode 00 hex normal (constant volume at 1khz) 04 hex super bass (constant volume at 2khz) higher resolution of loudness gain is possible: an lsb step results in a gain step of about 1/4 db. loudness increases the volume of low and high frequency signals, while keep- ing the amplitude of the reference frequency constant. the intended loudness has to be set according to the actual volume setting. because loudness intro- duces gain, it is not recommended to set loudness to a value that, in conjunction with volume, would result in an overall positive gain. the corner frequency for bass amplification can be set to two different values. in super bass mode, the corner frequency is shifted up. the point of constant vol- ume is shifted from 1 khz to 2 khz. loud_main table 3 ? 11: write registers on i 2 c subaddress 12 hex , continued register address function name preliminary data sheet msp 34x5g micronas 33 00 05 hex spatial effects loudspeaker channel bit[15:8] effect strength 7f hex enlargement 100% 3f hex enlargement 50% ... 01 hex enlargement 1.5% 00 hex effect off ff hex reduction 1.5% ... c0 hex reduction 50% 80 hex reduction 100% bit[7:4] spatial effect mode 0 hex stereo basewidth enlargement (sbe) and pseudo stereo effect (pse). (mode a) 2 hex stereo basewidth enlargement (sbe) only. (mode b) bit[3:0] spatial effect high-pass gain 0 hex max high-pass gain 2 hex 2/3 high-pass gain 4 hex 1/3 high-pass gain 6 hex min high-pass gain 8 hex automatic there are several spatial effect modes available: in mode a (low byte = 00 hex ), the spatial effect depends on the source mode. if the incoming signal is mono, pseudo stereo effect is active; for stereo signals, pseudo stereo effect and stereo basewidth enlargement is effective. the strength of the effect is controllable by the upper byte. a negative value reduces the stereo image. a strong spatial effect is recommended for small tv sets where loudspeaker spacing is rather close. for large screen tv sets, a more moderate spatial effect is recommended. in mode b, only stereo basewidth enlargement is effective. for mono input sig- nals, the pseudo stereo effect has to be switched on. it is worth mentioning that all spatial effects affect amplitude and phase response. with the lower 4 bits, the frequency response can be customized. a value of 0 hex yields a flat response for center signals (l = r) but a high-pass function for l or r only signals. a value of 6 hex has a flat response for l or r only signals but a low-pass function for center signals. by using 8 hex , the fre- quency response is automatically adapted to the sound material by choosing an optimal high-pass gain. s pat _ m a i n table 3 ? 11: write registers on i 2 c subaddress 12 hex , continued register address function name msp 34x5g preliminary data sheet 34 micronas scart output channel 00 07 hex volume scart1 output channel bit[15:8] volume table with 1 db step size 7f hex + 12 db (maximum volume) 7e hex + 11 db ... 74 hex + 1db 73 hex 0db 72 hex ? 1db ... 02 hex ? 113 db 01 hex ? 114 db 00 hex mute (reset condition) bit[7:5] higher resolution volume table 0 + 0db 1 + 0.125 db increase in addition to the volume table ... 7 + 0.875 db increase in addition to the volume table bit[4:0] 01 hex this must be 01 hex vol_scart1 scart switches and digital i/o pins 00 13 hex acb register defines the level of the digital output pins and the position of the scart switches bit[15] 0/1 low/high of digital output pin d_ctr_i/o_1 (modus[3]=0) bit[14] 0/1 low/high of digital output pin d_ctr_i/o_0 (modus[3]=0) bit[13:5] scart dsp input select xxxx00xx0 scart1 to dsp input (reset position) xxxx01xx0 mono to dsp input (sound a mono must be selected in the channel matrix mode for the corresponding output channels) xxxx10xx0 scart2 to dsp input xxxx11xx1 mute dsp input bit[13:5] scart1 output select xx00xxx0x undefined (reset position) xx01xxx0x scart2 input to scart1 output xx10xxx0x mono input to scart1 output xx11xxx0x scart1 da to scart1 output xx01xxx1x scart1 input to scart1 output xx11xxx1x mute scart1 output the reset position becomes active at the time of the first write transmission on the control bus to the audio processing part. by writing to the acb register first, the reset state can be redefined. acb_reg table 3 ? 11: write registers on i 2 c subaddress 12 hex , continued register address function name preliminary data sheet msp 34x5g micronas 35 beeper 00 14 hex beeper volume and frequency bit[15:8] beeper volume 00 hex off 7f hex maximum volume bit[7:0] beeper frequency 01 hex 16 hz (lowest) 40 hex 1khz ff hex 4khz beeper table 3 ? 11: write registers on i 2 c subaddress 12 hex , continued register address function name msp 34x5g preliminary data sheet 36 micronas 3.3.2.7. read registers on i 2 c subaddress 13 hex table 3 ? 12: read registers on i 2 c subaddress 13 hex register address function name quasi-peak detector readout 00 19 hex 00 1a hex quasi-peak detector readout left quasi-peak detector readout right bit[15:0] 0 hex ... 7fff hex values are 16 bit two ? s complement (only positive) qpeak_l qpeak_r msp 34x5g version readout registers 00 1e hex msp hardware version code bit[15:8] 02 hex msp 34x5g - b 8 a change in the hardware version code defines hardware optimizations that may have influence on the chip ? s behavior. the readout of this register is iden- tical to the hardware version code in the chip ? s imprint. msp major revision code bit[7:0] 07 hex msp 34x5g - b8 the major revision code of the msp 34x5g is 7. msp_hard msp_revision 00 1f hex msp product code bit[15:8] 0f hex msp 3415 g - b8 19 hex msp 3425 g - b8 2d hex msp 3445 g - b8 37 hex msp 3455 g - b8 41 hex msp 3465 g - b8 by means of the msp product code, the control processor is able to decide which tv sound standards have to be considered. msp rom version code bit[7:0] 44 hex msp 34x5g - a4 45 hex msp 34x5g - b5 46 hex msp 34x5g - b6 48 hex msp 34x5g - b8 a change in the rom version code defines internal software optimizations, that may have influence on the chip ? s behavior, e.g. new features may have been included. while a software change is intended to create no compatibility problems, customers that want to use the new functions can identify new msp 34x5g versions according to this number. to avoid compatibility problems with msp 3410b and msp 34x0d, an offset of 40 hex is added to the rom version code of the chip ? s imprint. msp_product msp_rom preliminary data sheet msp 34x5g micronas 37 3.4. programming tips this section describes the preferred method for initial- izing the msp 34x5g. the initialization is grouped into four sections: ? scart signal path (analog signal path) ? demodulator ? scart and i 2 s inputs ? output channels see fig. 2 ? 1 on page 8 for a complete signal flow. scart signal path 1. select analog input for the scart baseband pro- cessing (scart dsp input select) by means of the acb register. 2. select the source for each analog scart output (scart output select) by means of the acb regis- ter. demodulator for a complete setup of the tv sound processing from analog if input to the source selection, the following steps must be performed: 1. set modus register to the preferred mode and sound if input. 2. set preferred prescale (fm and nicam) values. 3. write standard select register. 4. if automatic sound select is not active: choose fm matrix repeatedly according to the sound mode indicated in the status register. scart and i 2 s inputs 1. set preferred prescale for scart. 2. set preferred prescale for i 2 s inputs (set to 0 db after reset). output channels 1. select the source channel and matrix for each out- put channel. 2. set audio baseband processing. 3. select volume for each output channel. 3.5. examples of minimum initialization codes initialization of the msp 34x5g according to these list- ings reproduces sound of the selected standard on the loudspeaker output. all numbers are hexadecimal. the examples have the following structure: 1. perform an i 2 c controlled reset of the ic. 2. write modus register (with automatic sound select). 3. set source selection for loudspeaker channel (with matrix set to stereo). 4. set prescale (fm and/or nicam and dummy fm matrix). 5. write standard select register. 6. set volume loudspeaker channel to 0 db. 3.5.1. b/g-fm (a2 or nicam) <80008000> // softreset <80000000> <801000302003> // modus-register: automatic = on <801200080320> // source sel. = (st or a) & ch. matr. = st <8012000e2403> // fm/am-prescale = 24 hex , fm-matrix = mono/sounda <801200105a00> // nicam-prescale = 5a hex <801000200003> // standard select: a2 b/g or nicam b/g or <801000200008> <801200007300> // loudspeaker volume 0 db 3.5.2. btsc-stereo <80008000> // softreset <80000000> <801000302003> // modus-register: automatic = on <801200080320> // source sel. = (st or a) & ch. matr. = st <8012000e2403> // fm/am-prescale = 24 hex , fm-matrix = sound a mono <801000200020> // standard select: btsc-stereo <801200007300> // loudspeaker volume 0 db 3.5.3. btsc-sap with sap at loudspeaker channel <80008000> // softreset <80000000> <801000302003> // modus-register: automatic = on <801200080320> // source sel. = (st or a) & ch. matr. = st <8012000e2403> // fm/am-prescale = 24 hex , fm-matrix = sound a mono <801000200021> // standard select: btsc-sap <801200007300> // loudspeaker volume 0 db msp 34x5g preliminary data sheet 38 micronas 3.5.4. fm-stereo radio <80008000> // softreset <80000000> <801000302003> // modus-register: automatic = on <801200080320> // source sel. = (st or a) & ch. matr. = st <8012000e2403> // fm/am-prescale = 24 hex , fm-matrix = sound a mono <801000200040> // standard select: fm-stereo-radio <801200007300> // loudspeaker volume 0 db 3.5.5. automatic standard detection a detailed software flow diagram is shown in fig. 3 ? 2 on page 39. <80008000> // softreset <80000000> <801000302003> // modus-register: automatic = on <801200080320> // source sel. = (st or a) & ch. matr. = st <8012000e2403> // fm/am-prescale = 24 hex , fm-matrix = sound a mono <801200105a00> // nicam-prescale = 5a hex <801000200001> // standard select: automatic standard detection // wait till standard result contains a value 07ff // if standard result contains 0000 // do some error handling // else <801200007300> // loudspeaker volume 0 db 3.5.6. software flow for interrupt driven status check a detailed software flow diagram is shown in fig. 3 ? 2 on page 39. if the d_ctr_i/o_1 pin of the msp 34x5g is con- nected to an interrupt input pin of the controller, the fol- lowing interrupt handler can be applied to be automati- cally called with each status change of the msp 34x5g. the interrupt handler may adjust the tv display according to the new status information. interrupt handler: <80 11 02 00 <81 dd dd> // read status // adjust tv-display with given status information // return from interrupt preliminary data sheet msp 34x5g micronas 39 fig. 3 ? 2: software flow diagram for a minimum demodulator setup for a european multistandard set applying the automatic sound select feature ([dpsoh set loudspeaker source select to "stereo or a" set headphone source select to "stereo or b" set scart_out source select to "stereo or a/b" set channel matrix mode for all outputs to "stereo" ! ! (start automatic standard detection) ! : ([dpsoh for the essential bits: >@ $xwrpdwlf6rxqg6hohfw rq [1] = 1 enable interrupt if status changes [8] = 0 ana_in1+ is selected define preference for automatic standard detection: [12] = 0 if 6.5 mhz, set secam-l [14:13] = 3 ignore 4.5 mhz carrier write fm/am-prescale write nicam-prescale " #$ % &'% ( ) # ** read status adjust tv-display if bilingual, adjust source select setting if required result = 0 ? set previous standard or set standard manually according picture information yes no expecting interrupt from msp msp 34x5g preliminary data sheet 40 micronas 4. specifications 4.1. outline dimensions fig. 4 ? 1: 64-pin plastic shrink dual inline package (psdip64) weight approximately 9.0 g dimensions in mm fig. 4 ? 2: 52-pin plastic shrink dual inline package (psdip52) weight approximately 5.5 g dimensions in mm fig. 4 ? 3: 80-pin plastic quad flat pack package (pqfp80) weight approximately 1.6 g dimensions in mm 132 33 64 57.7 0.1 0.8 0.2 3.8 0.1 3.2 0.2 1.778 1 0.05 31 x 1.778 = 55.1 0.1 0.48 0.06 20.3 0.5 0.28 0.06 18 0.05 19.3 0.1 spgs703000-1(p64)/1e 126 27 52 47.0 0.1 0.6 0.2 4.0 0.1 2.8 0.2 1.778 1 0.05 25 x 1.778 = 44.4 0.1 0.48 0.06 spgs703000-1(p52)/1e 16.3 1 0.28 0.06 14 0.1 15.6 0.1 15 x 0.8 = 12.0 0.1 0.8 0.8 41 64 24 1 65 80 40 25 0.1 3 0.2 spgs705000-3(p80)/1e 23.2 0.15 17.2 0.15 20 0.1 14 0.1 23 x 0.8 = 18.4 0.1 0.17 0.04 0.37 0.04 1.3 0.05 2.7 0.1 preliminary data sheet msp 34x5g micronas 41 fig. 4 ? 4: 64-pin plastic low-profile quad flat pack (plqfp64) weight approximately 0.35 g dimensions in mm fig. 4 ? 5: 44-pin plastic metric quad flat pack (pmqfp44) weight approximately 0.4 g dimensions in mm 10 0.1 1.75 1.75 49 64 116 17 32 33 48 d0025/3e 0.5 0.5 0.1 12 0.2 1.5 0.1 1.4 0.05 12 0.2 10 0.1 0.145 0.055 0.22 0.05 15 x 0.5 = 7.5 0.1 15 x 0.5 = 7.5 0.1 spgs706000-5(p44)/1e 34 44 1 11 12 22 23 33 0.1 0.8 0.8 13.2 0.2 13.2 0.2 0.17 0.06 2.15 0.2 2.0 0.1 0.34 0.05 10 0.1 10 0.1 10 x 0.8 = 8 0.1 10 x 0.8 = 8 0.1 msp 34x5g preliminary data sheet 42 micronas 4.2. pin connections and short descriptions nc = not connected; leave vacant lv = if not used, leave vacant dvss: if not used, connect to dvss x = obligatory; connect as described in circuit diagram ahvss: connect to ahvss pin no. pin name type connection (if not used) short description pqfp 80-pin plqfp 64-pin pmqfp 44-pin psdip 64-pin psdip 52-pin 164 ? 8 ? nc lv not connected 2 1 12 9 7 i2c_cl in/out x i 2 c clock 3 2 13 10 8 i2c_da in/out x i 2 c data 4 3 14 11 9 i2s_cl lv i 2 s clock 5 4 15 12 10 i2s_ws lv i 2 s word strobe 6 5 16 13 11 i2s_da_out lv i 2 s data output 7 6 17 14 12 i2s_da_in1 lv i 2 s1 data input 87 ? 15 13 adr_da lv adr data output 98 ? 16 14 adr_ws lv adr word strobe 10 9 18 17 15 adr_cl lv adr clock 11 ? ??? dvsup x digital power supply + 5 v 12 ? ??? dvsup x digital power supply + 5 v 13 10 19 18 16 dvsup x digital power supply + 5 v 14 ? 20 ?? dvss x digital ground 15 ? ??? dvss x digital ground 16 11 ? 19 17 dvss x digital ground 17 12 21 20 18 i2s_da_in2 lv i 2 s2-data input 18 13 ? 21 19 nc lv not connected 19 14 ? 22 ? nc lv not connected 20 15 ? 23 ? nc lv not connected 21 16 22 24 20 resetq in x power-on-reset 22 ? ??? nc lv not connected 23 ? ??? nc lv not connected 24 17 23 25 21 nc lv not connected 25 18 24 26 22 nc lv not connected 26 19 25 27 23 vref2 x reference ground 2 high-voltage part preliminary data sheet msp 34x5g micronas 43 27 20 26 28 24 dacm_r out lv loudspeaker out, right 28 21 27 29 25 dacm_l out lv loudspeaker out, left 29 22 ? 30 ? nc lv not connected 30 23 ? 31 26 nc lv not connected 31 24 ? 32 ? nc lv not connected 32 ? ??? nc lv not connected 33 25 ? 33 27 nc lv not connected 34 26 28 34 28 nc lv not connected 35 27 29 35 29 vref1 x reference ground 1 high-voltage part 36 28 30 36 30 sc1_out_r out lv scart 1 output, right 37 29 31 37 31 sc1_out_l out lv scart 1 output, left 38 30 32 38 32 nc lv not connected 39 31 33 39 33 ahvsup x analog power supply 8.0 v 40 32 34 40 34 capl_m x volume capacitor main 41 ? ??? nc lv not connected 42 ? ??? nc lv not connected 43 ? ??? ahvss x analog ground 44 33 35 41 35 ahvss x analog ground 45 34 36 42 36 agndc x analog reference voltage high-voltage part 46 ? ??? nc lv not connected 47 35 ? 43 ? nc lv not connected 48 36 ? 44 ? nc lv not connected 49 37 ? 45 ? nc lv not connected 50 38 ? 46 37 nc lv not connected 51 39 ? 47 38 nc lv not connected 52 40 ? 48 ? nc ahvss analog shield ground 53 41 37 49 39 sc2_in_l in lv scart 2 input, left 54 42 38 50 40 sc2_in_r in lv scart 2 input, right 55 43 39 51 ? asg ahvss analog shield ground 56 44 40 52 41 sc1_in_l in lv scart 1 input, left pin no. pin name type connection (if not used) short description pqfp 80-pin plqfp 64-pin pmqfp 44-pin psdip 64-pin psdip 52-pin msp 34x5g preliminary data sheet 44 micronas 57 45 41 53 42 sc1_in_r in lv scart 1 input, right 58 46 42 54 43 vreftop x reference voltage if a/d converter 59 ? ??? nc lv not connected 60 47 43 55 44 mono_in in lv mono input 61 ? ??? avss x analog ground 62 48 44 56 45 avss x analog ground 63 ? ??? nc lv not connected 64 ? ??? nc lv not connected 65 ? ??? avsup x analog power supply +5 v 66 49 1 57 46 avsup x analog power supply +5 v 67 50 2 58 47 ana_in1 + in lv if input 1 68 51 3 59 48 ana_in ? in lv if common 69 52 ? 60 49 nc lv not connected 70 53 4 61 50 testen in x test pin 71 54 5 62 51 xtal_in in x crystal oscillator 72 55 6 63 52 xtal_out out x crystal oscillator 73 56 7 64 1 tp lv test pin 74 57 ? 1 2 nc lv not connected 75 58 ? 2 ? nc lv not connected 76 59 ? 3 ? nc lv not connected 77 60 8 4 3 d_ctr_i/o_1 in/out lv d_ctr_i/o_1 78 61 9 5 4 d_ctr_i/o_0 in/out lv d_ctr_i/o_0 79 62 10 6 5 adr_sel in x i 2 c bus address select 80 63 11 7 6 standbyq in x standby (low-active) pin no. pin name type connection (if not used) short description pqfp 80-pin plqfp 64-pin pmqfp 44-pin psdip 64-pin psdip 52-pin preliminary data sheet msp 34x5g micronas 45 4.3. pin description pin numbers refer to the pqfp80 package pin 1, nc ? pin not connected pin 2, i2c_cl ? i 2 c clock input/output (fig. 4 ? 18) via this pin the i 2 c bus clock signal has to be supplied. the signal can be pulled down by the msp in case of wait conditions. pin 3, i2c_da ? i 2 c data input/output (fig. 4 ? 18) via this pin the i 2 c bus data is written to or read from the msp. pin 4, i2s_cl ? i 2 s clock input/output (fig. 4 ? 19) clock line for the i 2 s bus. in master mode, this line is driven by the msp; in slave mode, an external i 2 s clock has to be supplied. pin 5, i2s_ws ? i 2 s word strobe input/output (fig. 4 ? 19) word strobe line for the i 2 s bus. in master mode, this line is driven by the msp; in slave mode, an external i 2 s word strobe has to be supplied. pin 6, i2s_da_out ? i 2 s data output (fig. 4 ? 23) output of digital serial sound data of the msp on the i 2 s bus. pin 7, i2s_da_in1 ? i 2 s data input 1 (fig. 4 ? 17) first input of digital serial sound data to the msp via the i 2 s bus. pin 8, adr_da ? adr bus data output (fig. 4 ? 23) output of digital serial data to the drp 3510a via the adr bus. pin 9, adr_ws ? adr bus word strobe output (fig. 4 ? 23) word strobe output for the adr bus. pin 10, adr_cl ? adr bus clock output (fig. 4 ? 23) clock line for the adr bus. pins 11, 12, 13, dvsup* ? digital supply voltage power supply for the digital circuitry of the msp. must be connected to a +5-v power supply. pins 14, 15, 16, dvss* ? digital ground ground connection for the digital circuitry of the msp pin 17, i2s_da_in2 ? i 2 s data input 2 (fig. 4 ? 17) second input of digital serial sound data to the msp via the i 2 s bus. pins 18, 19, 20, nc ? pins not connected pin 21, resetq ? reset input (fig. 4 ? 11) in the steady state, high level is required. a low level resets the msp 34x0g. pins 22, 23, 24, 25, nc ? pins not connected pin 26, vref2 ? reference ground 2 reference analog ground. this pin must be connected separately to ground (ahvss). vref2 serves as a clean ground and should be used as the reference for analog connections to the loudspeaker and head- phone outputs. pins 27, 28, dacm_r/l ? loudspeaker outputs (fig. 4 ? 21) output of the loudspeaker signal. a 1nf capacitor to ahvss must be connected to these pins. the dc off- set on these pins depends on the selected loud- speaker volume. pins 29, 30, 31, 32, 33, 34, nc ? pins not connected pin 35, vref1 ? reference ground 1 reference analog ground. this pin must be connected separately to ground (ahvss). vref1 serves as a clean ground and should be used as the reference for analog connections to the scart outputs. pins 36, 37, sc1_out_r/l ? scart1 outputs (fig. 4 ? 22) output of the scart1 signal. connections to these pins must use a 100 ohm series resistor and are intended to be ac coupled. pin 38, nc ? pin not connected pin 39, ahvsup* ? analog power supply high voltage power is supplied via this pin for the analog circuitry of the msp (except if input). this pin must be connected to the +8v supply. pin 40, caplm ? volume capacitor loudspeakers (fig. 4 ? 24) a 10 f capacitor to ahvsup must be connected to this pin. it serves as smoothing filter for loudspeaker volume changes in order to suppress audible plops. the value of the capacitor can be lowered to 1 f if faster response is required. the area encircled by the trace lines should be minimized, keep traces as short as possible. this input is sensitive for magnetic induc- tion. pins 41, 42, nc ? pins not connected. pins 43, 44, ahvss* ? ground for analog power sup- ply high voltage ground connection for the analog circuitry of the msp (except if input). pins 45, agndc ? internal analog reference voltage this pin serves as the internal ground connection for the analog circuitry (except if input). it must be con- nected to the vref pins with a 3.3 f and a 100 nf capacitor in parallel. this pins shows a dc level of typ- ically 3.73 v. msp 34x5g preliminary data sheet 46 micronas pin 46, 47, 48, 49, 50, 51 nc ? pins not connected. pin 52, asg ? analog shield ground analog ground (ahvss) should be connected to this pin to reduce cross coupling between scart inputs. pins 53, 54, sc2_in_l/r ? scart2 inputs (fig. 4 ? 14) the analog input signal for scart2 is fed to this pin. analog input connection must be ac coupled. pin 55, asg ? analog shield ground analog ground (ahvss) should be connected to this pin to reduce cross coupling between scart inputs. pins 56, 57, sc1_in_l/r ? scart1 inputs (fig. 4 ? 14) the analog input signal for scart1 is fed to this pin. analog input connection must be ac coupled. pin 58, vreftop ? reference voltage if ad con- verter (fig. 4 ? 15) via this pin, the reference voltage for the if ad con- verter is decoupled. it must be connected to avss pins with a 10 f and a 100nf capacitor in parallel. traces must be kept short. pin 59, nc ? pin not connected pin 60, mono_in ? mono input (fig. 4 ? 14) the analog mono input signal is fed to this pin. analog input connection must be ac coupled. pins 61, 62, avss* ? ground for analog power supply voltage ground connection for the analog if input circuitry of the msp. pins 63, 64, nc ? pins not connected pins 65, 66, avsup* ? analog power supply voltage power is supplied via this pin for the analog if input cir- cuitry of the msp. this pin must be connected to the +5 v supply. pin 67, ana_in1+ ? if input 1 (fig. 4 ? 15) the analog sound if signal is supplied to this pin. inputs must be ac coupled. this pin is designed as symmetrical input: ana_in1+ is internally connected to one input of a symmetrical op amp, ana_in ? to the other. pin 68, ana_in ? ? if common (fig. 4 ? 15) this pin serves as a common reference for ana_in1/ 2+ inputs. pin 69, nc ? pin not connected pin 70, testen ? test enable pin (fig. 4 ? 12) this pin enables factory test modes. for normal opera- tion it must be connected to ground. pins71, 72, xtal_in, xtal_out ? crystal input and output pins (fig. 4 ? 20) these pins are connected to an 18.432 mhz crystal oscillator which is digitally tuned by integrated shunt capacitances. an external clock can be fed into xtal_in. the audio clock output signal aud_cl_out is derived form the oscillator. external capacitors at each crystal pin to ground (avss) are required. it should be verified by layout, that no supply current for the digital circuitry is flowing through the ground con- nection point. pin 73, tp ? te s t p i n pins 74, 75, 76, nc ? pins not connected pins 77, 78, d_ctr_i/o_1/0 ? digital control input/ output pins (fig. 4 ? 19) general purpose input/output pins. pin d_ctr_i/o_1 can be used as an interrupt request pin to the control- ler. pin 79, adr_sel ? i 2 c bus address select (fig. 4 ? 16) by means of this pin, one of 3 device addresses for the msp can be selected. the pin can be connected to ground (i 2 c device addresses 80/81 hex ), to +5v supply (84/85 hex ) or left open (88/89 hex ). pin 80, standbyq ? standby in normal operation, this pin must be high. if the msp 34x5g is switched off by first pulling standbyq low and then (after >1 s delay) switching off dvsup and avsup, but keeping ahvsup ( ? standby ? -mode ), the scart switches maintain their position and func- tion. * application note: all ground pins should be connected to one low-resis- tive ground plane. all supply pins should be connected separately with short and low-resistive lines to the power supply. decoupling capacitors from dvsup to dvss, avsup to avss, and ahvsup to ahvss are recommended as closely as possible to these pins. decoupling of dvsup and dvss is most important. we recommend using more than one capacitor. by choosing different values, the frequency range of active decoupling can be extended. in our application boards we use: 220 pf, 470 pf, 1.5 nf, and 10 f. t h e capacitor with the lowest value should be placed near- est to the dvsup and dvss pins. the asg pins should be connected as closely as pos- sible to the msp ground. if they are lead with the scart-inputs as shielding lines, they should not be connected to ground at the scart connector. preliminary data sheet msp 34x5g micronas 47 4.4. pin configurations fig. 4 ? 6: psdip64 package fig. 4 ? 7: psdip52 package 1 nc 2 nc 3 nc 4 d_ctr_i/o_1 5 d_ctr_i/o_0 6 adr_sel 7 standbyq 8 nc 9 i2c_cl 10 i2c_da 11 i2s_cl 12 i2s_ws 13 i2s_da_out 14 i2s_da_in1 15 adr_da 16 adr_ws tp 64 xtal_out 63 xtal_in 62 testen 61 nc 60 ana_in ? 59 ana_in1+ 58 avsup 57 avss 56 mono_in 55 vreftop 54 sc1_in_r 53 sc1_in_l 52 asg 51 sc2_in_r 50 sc2_in_l 49 17 adr_cl 18 dvsup 19 dvss 20 i2s_da_in2 21 nc 22 nc 23 nc 24 resetq 25 nc 26 nc nc 48 nc 47 nc 46 nc 45 nc 44 nc 43 agndc 42 ahvss 41 capl_m 40 ahvsup 39 msp 34x5g vref2 dacm_r dacm_l nc nc nc 38 37 36 35 34 33 27 28 29 30 31 32 nc sc1_out_l sc1_out_r vref1 nc nc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 tp nc d_ctr_i/o_1 d_ctr_i/o_0 adr_sel standbyq i2c_cl i2c_da i2s_cl i2s_ws i2s_da_out i2s_da_in1 adr_da adr_ws adr_cl dvsup xtal_out xtal_in testen nc ana_in ? ana_in1 + avsup avss mono_in vreftop sc1_in_r sc1_in_l sc2_in_r sc2_in_l nc nc dvss i2s_da_in2 nc resetq nc nc verf2 dacm_r dacm_l nc agndc ahvss capl_m ahvsup nc sc1_out_l sc1_out_r vref1 nc nc msp 34x5g msp 34x5g preliminary data sheet 48 micronas fig. 4 ? 8: pqfp80 package 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 1 2 3 4 5 6 7 8 9 101112131415161718192021222324 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 avsup avsup ana_in1 + ana_in ? nc testen xtal_in xtal_out tp nc nc nc d_ctr_i/o_1 d_ctr_i/o_0 adr_sel standbyq capl_m ahvsup nc sc1_out_l sc1_out_r vref1 nc nc nc nc nc nc dacm_l dacm_r vref2 nc nc avss avss mono_in nc vreftop sc1_in_r sc1_in_l asg nc sc2_in_r sc2_in_l asg nc nc nc nc nc nc agndc ahvss ahvss nc nc i2c_cl i2c_da i2s_cl i2s_ws i2s_da_out i2s_da_in1 adr_da adr_ws adr_cl nc dvsup dvsup dvsup dvss dvss dvss i2s_da_in2 nc nc nc resetq nc nc nc msp 34x5g preliminary data sheet msp 34x5g micronas 49 fig. 4 ? 9: plqfp64 package avsup ana_in1+ ana_in ? nc testen xtal_in xtal_out tp nc nc nc d_ctr_i/out1 d_ctr_i/out0 adr_sel standbyq nc capl_m ahvsup nc sc1_out_l sc1_out_r vref1 nc nc nc nc nc dacm_l dacm_r vref2 nc nc mono_in vreftop sc1_in_r sc1_in_l asg sc2_in_r sc2_in_l avss asg nc nc nc nc nc agndc ahvss i2c_da i2s_cl i2s_ws i2s_da_out i2s_da_in1 adr_da adr_ws i2c_cl adr_cl dvsup dvss i2s_da_in2 nc nc nc resetq msp 34x5g 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 12345678910111213141516 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 msp 34x5g preliminary data sheet 50 micronas fig. 4 ? 10: pmqfp44 package capl_m ahvss agndc sc2_in_l sc2_in_r asg sc1_in_l sc1_in_r vreftop mono_in avss resetq i2s_da_in2 dvss dvsup adr_cl i2s_da_in1 i2s_da_out i2s_ws i2s_cl i2c_da i2c_cl nc sc1_out_l sc1_out_r vref1 nc ahvsup dacm_l dacm_r vref2 nc nc ana_in1 + ana_in ? testen xtal_in xtal_out avsup tp d_ctr_i/o1 d_ctr_i/o0 adr_sel standbyq msp 34x5g 34 35 36 37 38 39 40 41 42 43 44 22 21 20 19 18 17 16 15 14 13 12 1234567891011 33 32 31 30 29 28 27 26 25 24 23 preliminary data sheet msp 34x5g micronas 51 4.5. pin circuits fig. 4 ? 11: input pin: resetq fig. 4 ? 12: input pin testen fig. 4 ? 13: input pin mono_in fig. 4 ? 14: input pins: sc2-1_in_l/r fig. 4 ? 15: input pins: vreftop, ana_in1+, ana_in ? fig. 4 ? 16: input pin: adr_sel fig. 4 ? 17: input pins: i2s_da_in1/2, standbyq dvss >300 k avsup 200 k 3.75 v 24 k 3.75 v 40 k d a ana_in1+ vreftop ana_in1 ? adr_sel gnd dvsup 23 k 23 k msp 34x5g preliminary data sheet 52 micronas fig. 4 ? 18: input/output pins: i2c_cl, i2c_da fig. 4 ? 19: input/output pins: i2s_cl, i2s_ws, d_ctr_i/o_1, d_ctr_i/o_0 fig. 4 ? 20: input/output pins xtal_in, xtal_out fig. 4 ? 21: output pins: dacm_r/l fig. 4 ? 22: output pins: sc_1_out_r/l fig. 4 ? 23: output pins: i2s_da_out, adr_da, adr_ws, adr_cl fig. 4 ? 24: capacitor pin: capl_m fig. 4 ? 25: pin: agndc n gnd dvsup p n gnd 3 ? 30 pf 500 k 3 ? 30 pf p n ahvsup 0...1.2 ma 3.3 k 26 pf 120 k 300 3.75 v dvsup p n gnd 0...2 v 3.75 v 125 k preliminary data sheet msp 34x5g micronas 53 4.6. electrical characteristics 4.6.1. absolute maximum ratings stresses beyond those listed in the ? absolute maximum ratings ? may cause permanent damage to the device. this is a stress rating only. functional operation of the device at these or any other conditions beyond those indicated in the ? recommended operating conditions/characteristics ? of this specification is not implied. exposure to absolute maximum ratings conditions for extended periods may affect device reliability. symbol parameter pin name min. max. unit t a ambient operating temperature ? 070 c t s storage temperature ? ? 40 125 c v sup1 first supply voltage ahvsup ? 0.3 9.0 v v sup2 second supply voltage dvsup ? 0.3 6.0 v v sup3 third supply voltage avsup ? 0.3 6.0 v dv sup23 voltage between avsup and dvsup avsup, dvsup ? 0.5 0.5 v p tot package power dissipation psdip64 psdip52 pqfp80 plqfp64 pmqfp44 ahvsup, dvsup, avsup 1300 1200 1000 960 960 mw mw mw mw mw v idig input voltage, all digital inputs ? 0.3 v sup2 +0.3 v i idig input current, all digital pins ? ? 20 +20 ma 1) v iana input voltage, all analog inputs scn_in_s, 2) mono_in ? 0.3 v sup1 +0.3 v i iana input current, all analog inputs scn_in_s, 2) mono_in ? 5+5ma 1) i oana output current, all scart outputs sc1_out_s 2) 3) , 4) 3) , 4) i oana output current, all analog outputs except scart outputs dacm_s 2) 3) 3) i cana output current, other pins connected to capacitors capl_m, agndc 3) 3) 1) positive value means current flowing into the circuit 2) ? n ? means ? 1 ? or ? 2 ? , ? s ? means ? l ? or ? r ? 3) the analog outputs are short-circuit proof with respect to first supply voltage and ground. 4) total chip power dissipation must not exceed absolute maximum rating. msp 34x5g preliminary data sheet 54 micronas 4.6.2. recommended operating conditions at t a = 0 to 70 c 4.6.2.1. general recommended operating conditions 4.6.2.2. analog input and output recommendations symbol parameter pin name min. typ. max. unit v sup1 first supply voltage (ahvsup = 8 v) ahvsup 7.6 8.0 8.7 v first supply voltage (ahvsup = 5v) 4.75 5.0 5.25 v v sup2 second supply voltage dvsup 4.75 5.0 5.25 v v sup3 third supply voltage avsup 4.75 5.0 5.25 v t stbyq1 standbyq setup time before turn-off of second supply voltage standbyq, dvsup 1 s symbol parameter pin name min. typ. max. unit c agndc agndc-filter-capacitor agndc ? 20% 3.3 f ceramic capacitor in parallel ? 20% 100 nf c insc dc-decoupling capacitor in front of scart inputs scn_in_s 1) ? 20% 330 nf v insc scart input level 2.0 v rms v inmono input level, mono input mono_in 2.0 v rms r lsc scart load resistance sc1_out_s 1) 10 k ? c lsc scart load capacitance 6.0 nf c vma main volume capacitor capl_m 10 f c fma main filter capacitor dacm_s 1) ? 10% 1 + 10% nf 1) ? n ? means ? 1 ? or ? 2 ? , ? s ? means ? l ? or ? r ? preliminary data sheet msp 34x5g micronas 55 4.6.2.3. recommendations for analog sound if input signal symbol parameter pin name min. typ. max. unit c vreftop vreftop-filter-capacitor vreftop ? 20% 10 f ceramic capacitor in parallel ? 20% 100 nf f if_fmtv analog input frequency range for tv applications ana_in1+, ana_in ? 09mhz f if_fmradio analog input frequency for fm-radio applications 10.7 mhz v if_fm analog input range fm/nicam 0.1 0.8 3 v pp v if_am analog input range am/nicam 0.1 0.45 0.8 v pp r fmni ratio: nicam carrier/fm carrier (unmodulated carriers) bg: i: ? 20 ? 23 ? 7 ? 10 0 0 db db r amni ratio: nicam carrier/am carrier (unmodulated carriers) ? 25 ? 11 0 db r fm ratio: fm-main/fm-sub satellite 7 db r fm1/fm2 ratio: fm1/fm2 german fm-system 7db r fc ratio: main fm carrier/ color carrier 15 ?? db r fv ratio: main fm carrier/ luma components 15 ?? db pr if passband ripple ?? 2db sup hf suppression of spectrum above 9.0 mhz (not for fm radio) 15 ? db fm max maximum fm-deviation (approx.) normal mode hdev2: high deviation mode hdev3: very high deviation mode 180 360 540 khz khz khz msp 34x5g preliminary data sheet 56 micronas 4.6.2.4. crystal recommendations symbol parameter pin name min. typ. max. unit general crystal recommendations f p crystal parallel resonance fre- quency at 12 pf load capacitance 18.432 mhz r r crystal series resistance 8 25 ? c 0 crystal shunt (parallel) capacitance 6.2 7.0 pf c l external load capacitance 1) xtal_in, xtal_out psdip approx. 1.5 p(l,m)qfpapprox. 3.3 pf pf crystal recommendations for master-slave applications (msp-clock must perform synchronization to i 2 s clock) f tol accuracy of adjustment ? 20 + 20 ppm d tem frequency variation versus temperature ? 20 + 20 ppm c 1 motional (dynamic) capacitance 19 24 ff f cl required open loop clock frequency (t amb = 25 c) 18.431 18.433 mhz 1) external capacitors at each crystal pin to ground are required. they are necessary to tune the open-loop fre- quency of the internal pll and to stabilize the frequency in closed-loop operation. due to different layouts, the accurate capacitor value should be determined with the customer pcb . the suggested values (1.5...3.3 pf) are figures based on experience and should serve as ? start value ? . to adjust the capacitor value, reset the msp and transfer only the following i 2 c-protocol: <80 10 00 20 00 60>. measure the frequency at pin adr_cl. measurement at xtal_in/out pins is not possible. change the capacitor value until the frequency matches 18.432/3 = 6.144 mhz as closely as possible. the higher the capacity, the lower the resulting clock frequency. note: to minimize adjustment tolerances for all msp-generations, it is strongly recommended to use the so- called msp-xtal-ref ics (available in all packages) for the capacitor adjustment. since all msp-xtal-ref ics do have an aud_cl_out-pin with the 18.432 mhz signal, this pin should be used for the capacitor adjustment instead of the adr_cl-pin. after the reset, no i 2 c-protocol should be transmitted. the aud_cl_out-signal is available at the following pins: plcc68 psdip64 psdip52 pqfp80 plqfp64 pmqfp44 2) pin 18 pin 1 pin 2 pin 74 pin 57 pin 8 2) for the msp-xtal-ref ic, the pmqfp44 pin functionality of the d_ctr_i/o1-pin has been changed to the audio_clock_out signal . if d_ctr_i/o1 is used in the customer application, this pin must be left open for the adjustment procedure. preliminary data sheet msp 34x5g micronas 57 crystal recommendations for fm / nicam applications (no msp-clock synchronization to i 2 s clock possible) f tol accuracy of adjustment ? 30 + 30 ppm d tem frequency variation versus temperature ? 30 + 30 ppm c 1 motional (dynamic) capacitance 15 ff f cl required open loop clock frequency (t amb = 25 c) 18.4305 18.4335 mhz crystal recommendations for all analog fm/am applications (no msp-clock synchronization to i 2 s clock possible) f tol accuracy of adjustment ? 100 + 100 ppm d tem frequency variation versus temperature ? 50 + 50 ppm f cl required open loop clock frequency (t amb = 25 c) 18.429 18.435 mhz amplitude recommendation for operation with external clock input (c load after reset typ. 22 pf) v xca external clock amplitude xtal_in 0.7 v pp symbol parameter pin name min. typ. max. unit msp 34x5g preliminary data sheet 58 micronas 4.6.3. characteristics at t a = 0 to 70 c, f clock = 18.432 mhz, v sup1 = 7.6 to 8.7 v, v sup2 = 4.75 to 5.25 v for min./max. values at t a = 60 c, f clock = 18.432 mhz, v sup1 = 8 v, v sup2 = 5 v for typical values, t j = junction temperature main (m) = loudspeaker channel 4.6.3.1. general characteristics symbol parameter pin name min. typ. max. unit test conditions supply i sup1a first supply current (active) (ahvsup = 8 v) ahvsup 17 11 25 16 ma ma vol. main and aux = 0 db vol. main and aux = - 30db first supply current (active) (ahvsup = 5 v) 11 8 17 11 ma ma vol. main and aux = 0 db vol. main and aux = -30 db i sup2a second supply current (active) dvsup 55 70 ma i sup3a third supply current (active) avsup 30 38 ma i sup1s first supply current (ahvsup = 8 v) ahvsup 5.6 7.7 ma standbyq = low first supply current (ahvsup = 5 v) 3.7 5.1 ma clock f clock clock input frequency xtal_in 18.432 mhz d clock clock high to low ratio 45 55 % t jitter clock jitter (verification not provided in production test) 50 ps v xtaldc dc-voltage oscillator 2.5 v t startup oscillator startup time at vdd slew-rate of 1 v/1 s xtal_in, xtal_out 0.4 2 ms preliminary data sheet msp 34x5g micronas 59 4.6.3.2. digital inputs, digital outputs symbol parameter pin name min. typ. max. unit test conditions digital input levels v digil digital input low voltage standbyq d_ctr_i/o_0/1 0.2 v sup2 v digih digital input high voltage 0.5 v sup2 z digi input impedance 5 pf i dleak digital input leakage current ? 11 a0v < u input < dvsup d_ctr_i/o_0/1: tri-state v digil digital input low voltage adr_sel 0.2 v sup2 v digih digital input high voltage 0.8 v sup2 i adrsel input current address select pin ? 500 ? 220 au adr_sel = dvss 220 500 au adr_sel = dvsup z testen input capacitance testen 5 pf i testen input low current ? 60 au testen = avss digital output levels v dctrol digital output low voltage d_ctr_i/o_0 d_ctr_i/o_1 0.4 v iddctr = 1 ma v dctroh digital output high voltage v sup2 ? 0.3 v iddctr = ? 1 ma msp 34x5g preliminary data sheet 60 micronas 4.6.3.3. reset input and power-up fig. 4 ? 26: power-up sequence symbol parameter pin name min. typ. max. unit test conditions resetq input levels v rhl reset high-low transition voltage resetq 0.3 0.4 v sup2 v rlh reset low-high transition voltage 0.45 0.55 v sup2 z res input capacitance 5 pf i res input high current 20 au resetq = dvsup 4.5 v internal reset t/ms resetq avsup dvsup high low t/ms t/ms note: the reset should not reach high level before the oscillator has started. this requires a reset delay of >2 ms 0.45 x dvsup means 2.25 volt with dvsup = 5.0 v 0.3...0.4 dvsup 0.45 dvsup high-to-low threshold low-to-high threshold reset delay >2 ms preliminary data sheet msp 34x5g micronas 61 4.6.3.4. i 2 c bus characteristics fig. 4 ? 27: i 2 c bus timing diagram symbol parameter pin name min. typ. max. unit test conditions v i2cil i 2 c-bus input low voltage i2c_cl, i2c_da 0.3 v sup2 v i2cih i 2 c-bus input high voltage 0.6 v sup2 t i2c1 i 2 c start condition setup time 120 ns t i2c2 i 2 c stop condition setup time 120 ns t i2c5 i 2 c-data setup time before rising edge of clock 55 ns t i2c6 i 2 c-data hold time after falling edge of clock 55 ns t i2c3 i 2 c-clock low pulse time i2c_cl 500 ns t i2c4 i 2 c-clock high pulse time 500 ns f i2c i 2 c-bus frequency 1.0 mhz v i2col i 2 c-data output low voltage i2c_cl, i2c_da 0.4 v i i2col = 3 ma i i2coh i 2 c-data output high leakage current 1.0 av i2coh = 5 v t i2col1 i 2 c-data output hold time after falling edge of clock 15 ns t i2col2 i 2 c-data output setup time before rising edge of clock 100 ns f i2c = 1 mhz i2c_cl i2c_da as input i2c_da as output t i2c1 t i2c5 t i2c6 t i2c2 t i2c4 t i2c3 1/f i2c t i2col2 t i2col1 msp 34x5g preliminary data sheet 62 micronas 4.6.3.5. i 2 s-bus characteristics symbol parameter pin name min. typ. max. unit test conditions v i2sil input low voltage i2s_cl i2s_ws i2s_da_in1/2 0.2 v sup2 v i2sih input high voltage 0.5 v sup2 z i2si input impedance 5 pf i leaki2s input leakage current ? 11 a0v < u input < dvsup v i2sol i 2 s output low voltage i2s_cl i2s_ws i2s_da_out 0.4 v i i2sol = 1 ma v i2soh i 2 s output high voltage v sup2 ? 0.3 vi i2soh = ? 1 ma f i2sows i 2 s-word strobe output frequency i2s_ws 32.0 khz f i2socl i 2 s-clock output frequency i2s_cl 1.024 2.048 mhz mhz i2s_config[0] = 0 i2s_config[0] = 1 r i2s10/i2s20 i 2 s-clock output high/low-ratio 0.9 1.0 1.1 t s_i2s i 2 s input setup time before rising edge of clock i2s_cl i2s_da_in1/2 12 ns for details see fig. 4 ? 28 ? i 2 s timing diagram ? t h_i2s i 2 s input hold time after rising edge of clock 40 ns t d_i2s i 2 s output delay time after falling edge of clock i2s_cl i2s_ws i2s_da_out 28 ns c l =30pf f i2sws i 2 s-word strobe input frequency i2s_ws 32.0 khz f i2scl i 2 s-clock input frequency i2s_cl 1.024 mhz r i2scl i 2 s-clock input high/low ratio 0.9 1.1 preliminary data sheet msp 34x5g micronas 63 fig. 4 ? 28: i 2 s timing diagram data: msb first, i 2 s master r lsb l lsb r lsb l lsb 16/32 bit right channel l lsb l lsb r msb r msb detail c i2s_ws i2s_cl i2s_da_in detail a modus[6] = 1 modus[6] = 0 detail b r lsb r lsb l msb l msb i2s_da_out 16/32 bit right channel 16/32 bit left channel 16/32 bit left channel 1/f i2sws i2s_cl detail c i2s_ws as input i2s_ws as output 1/f i2scl t s_i2s t d_i2s detail a,b i2s_cl i2s_da_out t d_i2s data: msb first, i 2 s slave r lsb l lsb r lsb l lsb 16, 18...32 bit right channel l lsb l lsb r msb r msb detail c i2s_ws i2s_cl i2s_da_in detail a modus[6] = 1 modus[6] = 0 detail b r lsb r lsb l msb l msb i2s_da_out 16, 18...32 bit right channel 16, 18...32 bit left channel 16,18...32 bit left channel 1/f i2sws t h_i2s t s_i2s i2s_da_in1/2 msp 34x5g preliminary data sheet 64 micronas 4.6.3.6. analog baseband inputs and outputs, agndc symbol parameter pin name min. typ. max. unit test conditions analog ground v agndc0 agndc open circuit voltage (ahvsup = 8 v) agndc 3.77 v r load 10 m ? agndc open circuit voltage (ahvsup = 5 v) 2.51 v r outagn agndc output resistance (ahvsup = 8 v) 70 125 180 k ? 3 v v agndc 4 v agndc output resistance (ahvsup = 5 v) 47 83 120 k ? analog input resistance r insc scart input resistance from t a = 0 to 70 c scn_in_s 1) 25 40 58 k ? f signal = 1 khz, i = 0.05 ma r inmono mono input resistance from t a = 0 to 70 c mono_in 152435k ? f signal = 1 khz, i = 0.1 ma audio analog-to-digital-converter v aicl analog input clipping level for analog-to-digital- conversion (ahvsup = 8 v) scn_in_s, 1) mono_in 2.00 2.25 v rms f signal = 1 khz analog input clipping level for analog-to-digital- conversion (ahvsup = 5 v) 1.13 1.51 v rms scart output r outsc scart output resistance scn_out_s 1) 200 200 330 460 500 ? ? f signal = 1 khz, i = 0.1 ma t j = 27 c t a = 0 to 70 c dv outsc deviation of dc-level at scart output from agndc voltage ? 70 + 70 mv a sctosc gain from analog input to scart output scn_in_s, 1) mono_in scn_out_s 1) ? 1.0 + 0.5 db f signal = 1 khz f rsctosc frequency response from analog input to scart output ? 0.5 + 0.5 db with resp. to 1 khz bandwidth: 0 to 20000 hz v outsc signal level at scart output (ahvsup = 8 v) scn_out_s 1) 1.8 1.9 2.0 v rms f signal = 1 khz volume 0 db full scale input from i 2 s signal level at scart output (ahvsup = 5v) 1.17 1.27 1.37 v rms 1) ? n ? means ? 1 ? or ? 2 ? ; ? s ? means ? l ? or ? r ? preliminary data sheet msp 34x5g micronas 65 4.6.3.7. sound if input 4.6.3.8. power supply rejection main output r outma main output resistance dacm_s 1) 2.1 2.1 3.3 4.6 5.0 k ? k ? f signal = 1 khz, i = 0.1 ma t j = 27 c t a = 0 to 70 c v outdcma dc-level at main-output (ahvsup = 8 v) 1.80 2.04 61 2.28 v mv volume 0 db volume ? 30 db dc-level at main-output (ahvsup = 5 v) 1.12 1.36 40 1.60 v mv volume 0 db volume ? 30 db v outma signal level at main-output (ahvsup = 8 v) 1.23 1.37 1.51 v rms f signal = 1 khz volume 0 db full scale input from i 2 s signal level at main-output (ahvsup = 5 v) 0.76 0.90 1.04 v rms 1) ? s ? means ? l ? or ? r ? symbol parameter pin name min. typ. max. unit test conditions r ifin input impedance ana_in1+, ana_in ? 1.5 6.8 2 9.1 2.5 11.4 k ? k ? gain agc = 20 db gain agc = 3 db dc vreftop dc voltage at vreftop vreftop 2.4 2.65 2.75 v dc ana_in dc voltage on if inputs ana_in1+, ana_in ? 1.3 1.5 1.7 v xtalk if crosstalk attenuation ana_in1+, ana_in ? 40 db f signal = 1 mhz input level = ? 2 dbr bw if 3 db bandwidth 10 mhz agc agc step width 0.85 db symbol parameter pin name min. typ. max. unit test conditions psrr: rejection of noise on ahvsup at 1 khz psrr agndc agndc 80 db from analog input to i 2 s output mono_in, scn_in_s 1) 70 db from analog input to scart output mono_in, scn_in_s 1) scn_out_s 1) 70 db from i 2 s input to scart output scn_out_s 1) 60 db from i 2 s input to main or aux output dacm_s 1) 80 db 1) ? n ? means ? 1 ? or ? 2 ? ; ? s ? means ? l ? or ? r ? symbol parameter pin name min. typ. max. unit test conditions msp 34x5g preliminary data sheet 66 micronas 4.6.3.9. analog performance symbol parameter pin name min. typ. max. unit test conditions specifications for ahvsup = 8 v snr signal-to-noise ratio from analog input to i 2 s output mono_in, scn_in_s 1) 85 88 db input level = ? 20 db with resp. to v aicl , f sig = 1 khz, unweighted 20 hz...16 khz from analog input to scart output mono_in, scn_in_s 1) scn_out_s 1) 93 96 db input level = ? 20 db, f sig = 1 khz, unweighted 20 hz...20 khz from i 2 s input to scart output scn_out_s 1) 85 88 db input level = ? 20 db, f sig = 1 khz, unweighted 20 hz...16 khz from i 2 s input to main output for analog volume at 0 db for analog volume at ? 30 db dacm_s 1) 85 78 88 83 db db input level = ? 20 db, f sig = 1 khz, unweighted 20 hz...16 khz thd total harmonic distortion from analog input to i 2 s output mono_in, scn_in_s 1) 0.01 0.03 % input level = ? 3 dbr with resp. to v aicl , f sig = 1 khz, unweighted 20 hz...16 khz from analog input to scart output mono_in, scn_in_s scn_out_s 1) 0.01 0.03 % input level = ? 3 dbr, f sig = 1 khz, unweighted 20 hz...20 khz from i 2 s input to scart output scn_out_s 1) 0.01 0.03 % input level = ? 3 dbr, f sig = 1 khz, unweighted 20 hz...16 khz from i 2 s input to main output dacm_s 1) 0.01 0.03 % input level = ? 3 dbr, f sig = 1 khz, unweighted 20 hz...16 khz 1) ? n ? means ? 1 ? or ? 2 ? ; ? s ? means ? l ? or ? r ? preliminary data sheet msp 34x5g micronas 67 specifications for ahvsup = 5 v snr signal-to-noise ratio from analog input to i 2 s output mono_in, scn_in_s 1) 82 85 db input level = ? 20 db with resp. to v aicl , f sig = 1 khz, unweighted 20 hz...16 khz from analog input to scart output mono_in, scn_in_s 1) scn_out_s 1) 90 93 db input level = ? 20 db, f sig = 1 khz, unweighted 20 hz...20 khz from i 2 s input to scart output scn_out_s 1) 82 85 db input level = ? 20 db, f sig = 1 khz, unweighted 20 hz...16 khz from i 2 s input to main output for analog volume at 0 db for analog volume at ? 30 db dacm_s 1) 82 75 85 80 db db input level = ? 20 db, f sig = 1 khz, unweighted 20 hz...16 khz thd total harmonic distortion from analog input to i 2 s output mono_in, scn_in_s 1) 0.03 0.1 % input level = ? 3 dbr with resp. to v aicl , f sig = 1 khz, unweighted 20 hz...16 khz from analog input to scart output mono_in, scn_in_s scn_out_s 1) 0.1 % input level = ? 3 dbr, f sig = 1 khz, unweighted 20 hz...20 khz from i 2 s input to scart output scn_out_s 1) 0.1 % input level = ? 3 dbr, f sig = 1 khz, unweighted 20 hz...16 khz from i 2 s input to main output dacm_s 1) 0.1 % input level = ? 3 dbr, f sig = 1 khz, unweighted 20 hz...16 khz 1) ? n ? means ? 1 ? or ? 2 ? ; ? s ? means ? l ? or ? r ? symbol parameter pin name min. typ. max. unit test conditions msp 34x5g preliminary data sheet 68 micronas crosstalk specifications for ahvsup = 8 v and 5 v xtalk crosstalk attenuation input level = ? 3 db, f sig = 1 khz, unused analog inputs connected to ground by z < 1 k ? between left and right channel within scart input/output pair (l r, r l) scn_in 1) sc1_out sc1_in or sc2_in i 2 s output sc3_in i 2 s output i 2 s input sc1_out 80 80 80 80 db db db db unweighted 20 hz...20 khz between left and right channel within main or aux output pair i 2 s input dacm 75 db unweighted 20 hz...16 khz between scart input/output pairs d = disturbing program o = observed program d: mono/scn_in 1) sc1_out o: mono/scn_in 1) sc1_out d: mono/scn_in 1) sc1_out or unsel. o: mono/scn_in 1) i 2 s output d: mono/scn_in 1) sc1_out o: i 2 s input sc1_out d: mono/scn_in 1) unselected o: i 2 s input sc1_out 100 95 100 100 db db db db (unweighted 20 hz...20 khz same signal source on left and right disturbing channel, effect on each observed output channel crosstalk between main and aux output pairs i 2 s input dacm 90 db (unweighted 20 hz...16 khz) same signal source on left and right disturbing channel, effect on each observed output channel xtalk crosstalk from main or aux output to scart output and vice versa d = disturbing program o = observed program d: mono/scn_in/dsp 1) sc1_out o: i 2 s input dacm d: mono/scn_in/dsp 1) sc1_out o: i 2 s input dacm d: i 2 s input dacm o: mono/scn_in 1) sc1_out d: i 2 s input dacm o: i 2 s input sc1_out 80 85 95 95 db db db db (unweighted 20 hz...20 khz) same signal source on left and right disturbing channel, effect on each observed output channel scart output load resistance 10 k ? scart output load resistance 30 k ? 1) ? n ? means ? 1 ? or ? 2 ? ; ? s ? means ? l ? or ? r ? symbol parameter pin name min. typ. max. unit test conditions preliminary data sheet msp 34x5g micronas 69 4.6.3.10. sound standard dependent characteristics symbol parameter pin name min. typ. max. unit test conditions nicam characteristics (msp standard code = 8) dv nicamout tolerance of output voltage of nicam baseband signal dacm_s, sc1_out_s 1) ? 1.5 + 1.5 db 2.12 khz, modulator input level = 0 dbref s/n nicam s/n of nicam baseband signal 72 db nicam: ? 6 db, 1 khz, rms unweighted 0 to 15 khz, vol = 9 db nic_presc = 7f hex output level 1 v rms at dacm_s thd nicam total harmonic distortion + noise of nicam baseband signal 0.1 % 2.12 khz, modulator input level = 0 dbref ber nicam nicam: bit error rate 1 10 ? 7 fm + nicam, norm conditions fr nicam nicam frequency response, 20...15000 hz ? 1.0 + 1.0 db modulator input level = ? 12 db dbref; rms xtalk nicam nicam crosstalk attenuation (dual) 80 db sep nicam nicam channel separation (stereo) 80 db fm characteristics (msp standard code = 3) dv fmout tolerance of output voltage of fm demodulated signal dacm_s, sc1_out_s 1) ? 1.5 + 1.5 db 1 fm-carrier, 50 s, 1 khz, 40 khz deviation; rms s/n fm s/n of fm demodulated signal 73 db 1 fm-carrier 5.5 mhz, 50 s, 1 khz, 40 khz deviation; rms, unweighted 0 to 15 khz (for s/n); full input range, fm-pres- cale = 46 hex , vol = 0 db output level 1 v rms at dacm_s thd fm total harmonic distortion + noise of fm demodulated signal 0.1 % fr fm fm frequency responses, 20...15000 hz ? 1.0 + 1.0 db 1 fm-carrier 5.5 mhz, 50 s, modulator input level = ? 14.6 dbref; rms xtalk fm fm crosstalk attenuation (dual) 80 db 2 fm-carriers 5.5/5.74 mhz, 50 s, 1 khz, 40 khz deviation; bandpass 1 khz sep fm fm channel separation (stereo) 50 db 2 fm-carriers 5.5/5.74 mhz, 50 s, 1 khz, 40 khz deviation; rms am characteristics (msp standard code = 9) s/n am(1) s/n of am demodulated signal measurement condition: rms/flat dacm_s, sc1_out_s 1) 55 db sif level: 0.1 ? 0.8 v pp am-carrier 54% at 6.5 mhz vol = 0 db, fm/am prescaler set for output = 0.5 v rms at loudspeaker out; standard code = 09 hex no video/chroma components s/n am(2) s/n of am demodulated signal measurement condition: qp/ccir 45 db thd am total harmonic distortion + noise of am demodulated signal 0.6 % fr am am frequency response 50...12000 hz ? 2.5 + 1.0 db 1) ? s ? means ? l ? or ? r ? msp 34x5g preliminary data sheet 70 micronas btsc characteristics (msp standard code = 20 hex , 21 hex ) s/n btsc s/n of btsc stereo signal s/n of btsc-sap signal dacm_s, sc1_out_s 1) 68 57 db db 1 khz l or r or sap, 100% modulation, 75 s deempha- sis, rms unweighted 0 to 15 khz thd btsc thd + n of btsc stereo signal thd + n of btsc sap signal 0.1 0.5 % % 1 khz l or r or sap, 100% 75 s eim 2) , dbx nr or mnr, rms unweighted 0 to 15 khz fr dbx frequency response of btsc stereo, 50 hz...12 khz frequency response of btsc- sap, 50 hz...9 khz ? 1.0 ? 1.0 1.0 1.0 db db l or r or sap, 1%...66% eim 2) , dbx nr fr mnr frequency response of btsc stereo, 50 hz...12 khz ? 2.0 2.0 db l or r 5%...66% eim 2) , mnr frequency response of btsc- sap, 50 hz...9 khz ? 2.0 2.0 db sap, white noise, 10% modu- lation, mnr xtalk btsc stereo sap sap stereo 76 80 db db 1 khz l or r or sap, 100% modulation, 75 s deempha- sis, bandpass 1 khz sep dbx stereo separation dbx nr 50 hz...10 khz 50 hz...12 khz 35 30 db db l or r 1%...66% eim 2) , dbx nr sep mnr stereo separation mnr 30 db l = 300 hz, r = 3.1 khz 14% modulation, mnr fm pil pilot deviation threshold stereo off on stereo on off ana_in1+ 3.2 1.2 3.5 1.5 khz khz 4.5 mhz carrier modulated with f h = 15.734 khz sif level = 100 mv pp indication: status bit[6] f pilot pilot frequency range 15.563 15.843 khz standard btsc stereo signal, sound carrier only 1) ? s ? means ? l ? or ? r ? 2) eim refers to 75- s equivalent input modulation. it is defined as the audio-signal level which results in a stated percentage modulation, when the dbx encoding process is replaced by a 75- s preemphasis network. symbol parameter pin name min. typ. max. unit test conditions preliminary data sheet msp 34x5g micronas 71 btsc characteristics (msp standard code = 20 hex , 21 hex ) with a minimum if input signal level of 70 mvpp (measured without any video/chroma signal components) s/n btsc s/n of btsc stereo signal s/n of btsc-sap signal dacm_s, sc1_out_s 1) 64 55 db db 1 khz l or r or sap, 100% modulation, 75 s deempha- sis, rms unweighted 0 to 15 khz thd btsc thd + n of btsc stereo signal thd + n of btsc sap signal 0.15 0.8 % % 1 khz l or r or sap, 100% 75 s eim 2) , dbx nr or mnr, rms unweighted 0 to 15 khz fr dbx frequency response of btsc stereo, 50 hz...12 khz frequency response of btsc- sap, 50 hz...9 khz ? 1.0 ? 1.0 1.0 1.0 db db l or r or sap, 1%...66% eim 2) , dbx nr fr mnr frequency response of btsc stereo, 50 hz...12 khz ? 2.0 2.0 db l or r 5%...66% eim 2) , mnr frequency response of btsc- sap, 50 hz...9 khz ? 2.0 2.0 db sap, white noise, 10% modu- lation, mnr xtalk btsc stereo sap sap stereo 75 75 db db 1 khz l or r or sap, 100% modulation, 75 s deempha- sis, bandpass 1 khz sep dbx stereo separation dbx nr 50 hz...10 khz 50 hz...12 khz 35 30 db db l or r 1%...66% eim 2) , dbx nr sep mnr stereo separation mnr 30 db l = 300 hz, r = 3.1 khz 14% modulation, mnr 1) ? s ? means ? l ? or ? r ? 2) eim refers to 75- s equivalent input modulation. it is defined as the audio-signal level which results in a stated percentage modulation, when the dbx encoding process is replaced by a 75- s preemphasis network. symbol parameter pin name min. typ. max. unit test conditions msp 34x5g preliminary data sheet 72 micronas eia-j characteristics (msp standard code = 30 hex ) s/n eiaj s/n of eia-j stereo signal s/n of eia-j sub-channel dacm_s, sc1_out_s 1) 60 60 db db 1 khz l or r, 100% modulation, 75 s deemphasis, rms unweighted 0 to 15 khz thd eiaj thd + n of eia-j stereo signal thd + n of eia-j sub-channel 0.2 0.3 % % fr eiaj frequency response of eia-j stereo, 50 hz...12 khz frequency response of eia-j sub-channel, 50 hz...12 khz ? 1.0 ? 1.0 1.0 1.0 db db 100% modulation, 75 s deemphasis xtalk eiaj main sub sub main 66 80 db db 1 khz l or r, 100% modulation, 75 s deemphasis, bandpass 1 khz sep eiaj stereo separation 50 hz...5 khz 50 hz...10 khz 35 28 db db eia-j stereo signal, l or r 100% modulation fm-radio characteristics (msp standard code = 40 hex ) s/n ukw s/n of fm-radio stereo signal dacm_s, sc1_out_s 1) 68 db 1 khz l or r, 100% modulation, 75 s deemphasis, rms unweighted 0 to 15 khz thd ukw thd + n of fm-radio stereo signal 0.1 % fr ukw frequency response of fm-radio stereo 50 hz...15 khz ? 1.0 + 1.0 db l or r, 1%...100% modulation, 75 s deemphasis sep ukw stereo separation 50 hz...15 khz 45 db f pilot pilot frequency range ana_in1+ 18.844 19.125 khz standard fm radio stereo signal 1) ? s ? means ? l ? or ? r ? symbol parameter pin name min. typ. max. unit test conditions preliminary data sheet msp 34x5g micronas 73 5. appendix a: overview of tv sound standards 5.1. nicam 728 table 5 ? 1: summary of nicam 728 sound modulation parameters specification i b/g l d/k carrier frequency of digital sound 6.552 mhz 5.85 mhz 5.85 mhz 5.85 mhz transmission rate 728 kbit/s type of modulation differentially encoded quadrature phase shift keying (dqpsk) spectrum shaping roll-off factor by means of roll-off filters 1.0 0.4 0.4 0.4 carrier frequency of analog sound component 6.0 mhz fm mono 5.5 mhz fm mono 6.5 mhz am mono 6.5 mhz fm mono terrestrial cable power ratio between vision carrier and analog sound carrier 10 db 13 db 10 db 16 db 13 db power ratio between analog and modulated digital sound carrier 10 db 7 db 17 db 11 db china/ hungary poland 12 db 7 db table 5 ? 2: summary of nicam 728 sound coding characteristics characteristics values audio sampling frequency 32 khz number of channels 2 initial resolution 14 bit/sample companding characteristics near instantaneous, with compression to 10 bits/sample in 32-samples (1 ms) blocks coding for compressed samples 2 ? s complement preemphasis ccitt recommendation j.17 (6.5 db attenuation at 800 hz) audio overload level +12 dbm measured at the unity gain frequency of the preemphasis network (2 khz) msp 34x5g preliminary data sheet 74 micronas 5.2. a2 systems table 5 ? 3: key parameters for a2 systems of standards b/g, d/k, and m characteristics sound carrier fm1 sound carrier fm2 tv-sound standard b/g d/k m b/g d/k m carrier frequency in mhz 5.5 6.5 4.5 5.7421875 6.2578125 6.7421875 5.7421875 4.724212 vision/sound power difference 13 db 20 db sound bandwidth 40 hz to 15 khz preemphasis 50 s75 s50 s75 s frequency deviation (nom/max) 27 / 50 khz 17 / 25 khz 27 / 50 khz 15 / 25 khz transmission modes mono transmission mono mono stereo transmission (l + r)/2 (l + r)/2 r (l ? r)/2 dual sound transmission language a language b identification of transmission mode pilot carrier frequency 54.6875 khz 55.0699 khz max. deviation portion 2.5 khz type of modulation / modulation depth am / 50% modulation frequency mono: unmodulated stereo: 117.5 hz dual: 274.1 hz 149.9 hz 276.0 hz preliminary data sheet msp 34x5g micronas 75 5.3. btsc-sound system 5.4. japanese fm stereo system (eia-j) table 5 ? 4: key parameters for btsc-sound systems aural carrier btsc-mpx-components (l + r) pilot (l ? r) sap prof. ch. carrier frequency (f hntsc = 15.734 khz) (f hpal = 15.625 khz) 4.5 mhz baseband f h 2 f h 5 f h 6.5 f h sound bandwidth in khz 0.05 - 15 0.05 - 15 0.05 - 12 0.05 - 3.4 preemphasis 75 s dbx dbx 150 s max. deviation to aural carrier 73 khz (total) 25 khz 1) 5khz 50khz 1) 15 khz 3 khz max. freq. deviation of subcarrier modulation type am 10 khz fm 3khz fm 1) sum does not exceed 50 khz due to interleaving effects table 5 ? 5: key parameters for japanese fm-stereo sound system eia-j aural carrier fm eia-j-mpx-components (l + r) (l ? r) identification carrier frequency (f h = 15.734 khz) 4.5 mhz baseband 2 f h 3.5 f h sound bandwidth 0.05 - 15 khz 0.05 - 15 khz ? preemphasis 75 s75 s none max. deviation portion to aural carrier 47 khz 25 khz 20 khz 2 khz max. freq. deviation of subcarrier modulation type 10 khz fm 60% am transmitter-sided delay 20 s0 s0 s mono transmission l + r ? unmodulated stereo transmission l + rl ? r 982.5 hz bilingual transmission language a language b 922.5 hz msp 34x5g preliminary data sheet 76 micronas 5.5. fm satellite sound 5.6. fm-stereo radio table 5 ? 6: key parameters for fm satellite sound carrier frequency maximum fm deviation sound mode bandwidth deemphasis 6.5 mhz 85 khz mono 15 khz 50 s 7.02/7.20 mhz 50 khz mono/stereo/bilingual 15 khz adaptive 7.38/7.56 mhz 50 khz mono/stereo/bilingual 15 khz adaptive 7.74/7.92 mhz 50 khz mono/stereo/bilingual 15 khz adaptive table 5 ? 7: key parameters for fm-stereo radio systems aural carrier fm-radio-mpx-components (l + r) pilot (l ? r) rds/ari carrier frequency (f p = 19 khz) 10.7 mhz baseband f p 2 f p 3 f h sound bandwidth in khz 0.05 - 15 0.05 - 15 preemphasis: ? usa ? europe 75 s 50 s 75 s 50 s max. deviation to aural carrier 75 khz (100%) 90% 1) 10% 90% 1) 5% 1) sum does not exceed 90% due to interleaving effects. preliminary data sheet msp 34x5g micronas 77 6. appendix b: manual/compatibility mode to adapt the modes of the standard select regis- ter to individual requirements and for reasons of com- patibility to the msp 34x5d, the msp 34x5g offers an manual/compatibility mode, which provides sophis- ticated programming of the msp 34x5g. using the standard select register generally pro- vides a more economic way to program the msp 34x5g and will result in optimal behavior. there- fore, it is not recommend to use the manual/com- patibility mode. in those cases, where the msp 34x5d is to be substituted by the msp 34x5g, the tips given in section 6.9. on page 91 have to be obeyed by the controller software. 6.1. demodulator write and read registers for manual/compatibility mode table 6 ? 1: demodulator write registers; subaddress: 10 hex ; these registers are not readable! demodulator write registers address (hex) msp- version description reset mode page auto_fm/am 00 21 3415, 3455 1. modus[0]=1 (automatic sound select): switching level threshold of automatic switching between nicam and fm/am in case of bad nicam reception 2. modus[0]=0 (manual mode): activation and configuration of automatic switching between nicam and fm/am in case of bad nicam reception 00 00 79 a2_threshold 00 22 all a2 stereo identification threshold 00 19 hex 81 cm_threshold 00 24 all carrier-mute threshold 00 2a hex 81 ad_cv 00 bb all sif-input selection, configuration of agc, and carrier-mute function 00 00 82 mode_reg 00 83 3415, 3455 controlling of msp-demodulator and interface options. as soon as this register is applied, the msp 34x5g works in the msp 34x5d compatibility mode. warning: in this mode, btsc, eia-j, and fm-radio are disabled. only msp 34x5d features are available; the use of modus and status register is not allowed. the msp 34x5g is reset to the normal mode by first programming the modus register followed by transmitting a valid standard code to the standard selection register. 00 00 83 fir1 fir2 00 01 00 05 fir1-filter coefficients channel 1 (6 ? 8 bit) fir2-filter coefficients channel 2 (6 ? 8 bit), + 3 ? 8 bit offset (total 72 bit) 00 00 85 dco1_lo dco1_hi dco2_lo dco2_hi 00 93 00 9b 00 a3 00 ab increment channel 1 low part increment channel 1 high part increment channel 2 low part increment channel 2 high part 00 00 85 note: all registers except auto_fm/am, a2_threshold, and cm_threshold are initialized during standard selection and are automatically updated when automatic sound select (modus[0]=1) is on. msp 34x5g preliminary data sheet 78 micronas 6.2. dsp write and read registers for manual/compatibility mode table 6 ? 2: demodulator read registers; subaddress: 11 hex ; these registers are not writable! demodulator read registers address (hex) msp- version description page c_ad_bits 00 23 3415, 3455 nicam-sync bit, nicam-c-bits, and three lsbs of additional data bits 87 add_bits 00 38 nicam: bit [10:3] of additional data bits 87 cib_bits 00 3e nicam: cib1 and cib2 control bits 87 error_rate 00 57 nicam error rate, updated with 182 ms 88 pll_caps 02 1f not for customer use. 88 agc_gain 02 1e not for customer use. 88 table 6 ? 3: dsp-write registers; subaddress: 12 hex , all registers are readable as well write register address (hex) bits operational modes and adjustable range reset mode page volume scart1 channel: ctrl. mode 00 07 [7:0] [linear mode / logarithmic mode] 00 hex 89 fm fixed deemphasis 00 0f [15:8] [50 s, 75 s, j17, off] 50 s89 fm adaptive deemphasis [7:0] [off, wp1] off 89 identification mode 00 15 [7:0] [b/g, m] b/g 90 fm dc notch 00 17 [7:0] [on, off] on 90 table 6 ? 4: dsp read registers; subaddress: 13 hex , all registers are not writable additional read registers address (hex) bits output range page stereo detection register for a2 stereo systems 00 18 [15:8] [80 hex ... 7f hex ] 8 bit two ? s complement 90 dc level readout fm1/ch2-l 00 1b [15:0] [8000 hex ... 7fff hex ] 16 bit two ? s complement 90 dc level readout fm2/ch1-r 00 1c [15:0] [8000 hex ... 7fff hex ] 16 bit two ? s complement 90 preliminary data sheet msp 34x5g micronas 79 6.3. manual/compatibility mode: description of demodulator write registers 6.3.1. automatic switching between nicam and analog sound in case of bad nicam reception or loss of the nicam-carrier, the msp 34x5g offers an automatic switching (fall back) to the analog sound (fm/am- mono), without the necessity for the controller of reading and evaluating any parameters. if a proper nicam sig- nal returns, switching back to this source is performed automatically as well. the feature evaluates the nicam error_rate and switches, if necessary, all output channels which are assigned to the nicam-source, to the analog source, and vice versa. an appropriate hysteresis algorithm avoids oscillating effects (see fig. 6 ? 1). status[9] and c_ad_bits[11] (addr: 0023 hex) provide information about the actual nicam-fm/am-status. fig. 6 ? 1: hysteresis for automatic switching 6.3.1.1. function in automatic sound select mode the automatic sound select feature (modus[0]=1) includes the procedure mentioned above. by default, the internal error_rate threshold is set to 700 dec . i.e.: ? nicam analog sound if error_rate > 700 ? analog sound nicam if error_rate < 700/2 the error_rate value of 700 corresponds to a ber of approximately 5.46*10 -3 /s. individual configuration of the threshold can be done using table 6 ? 5. however, the internal setting used by the standard selection is recommended. the optimum nicam sound can be assigned to the msp output channels by selecting one of the ? stereo or a/b ? , ? stereo or a ? , or ? stereo or b ? source chan- nels 6.3.1.2. function in manual mode if the manual mode (modus[0]=0) is required, the activation and configuration of the automatic switching feature has to be done as described in table 6 ? 6. note, that the channel matrix of the corresponding out- put-channels must be set according to the nicam-mode and need not to be changed in the fm/ am-fallback case. example: required threshold = 500: bits[10:1] = 00 1111 1010 error_rate selected sound nicam analog sound threshold threshold/2 table 6 ? 5: coding of automatic nicam/analog sound switching; automatic sound select is on (modus[0] = 1) mode description auto_fm [11:0] addr. = 00 21 hex error_rate- threshold/dec source select: input at nicam path 1) 1 default automatic switching with internal threshold bit[11:0] = 0 700 nicam or fm/am, depending on error_rate 2 automatic switching with external threshold (customizing of automatic sound select) bit[11] = 0 bit[10:1] = 25...1000 = threshold/2 bit[0] = 1 set by customer; recommended range: 50...2000 3 forced analog mono bit[11] = 1 bit[10:1] = ignored bit[0] = 1 always fm/am 1) the nicam path may be assigned to ? stereo or a/b ? , ? stereo or a ? , or ? stereo or b ? source channels (see table 2 ? 1 on page 11). msp 34x5g preliminary data sheet 80 micronas table 6 ? 6: coding of automatic nicam/analog sound switching; automatic sound select is off (modus[0] = 0) mode description auto_fm [11:0] addr. = 00 21 hex error_rate- threshold/dec source select: input at nicam path 0 reset status forced nicam (automatic switching disabled) bit[11] = 0 bit[10:1] = 0 bit[0] = 0 none always nicam; mute in case of no nicam available 1 automatic switching with internal threshold (default, if automatic sound select is on) bit[11] = 0 bit[10:1] = 0 bit[0] = 1 700 nicam or fm/am, depending on error_rate 2 automatic switching with external threshold (customizing of automatic sound select) bit[11] = 0 bit[10:1] = 25...1000 = threshold/2 bit[0] = 1 set by customer; recommended range: 50...2000 3 forced analog mono (automatic switching disabled) bit[11] = 1 bit[10:1] = 0 bit[0] = 1 none always fm/am preliminary data sheet msp 34x5g micronas 81 6.3.2. a2 threshold the threshold between stereo/bilingual and mono identification for the a2 standard has been made pro- grammable according to the user ? s preferences. an internal hysteresis ensures robustness and stability. 6.3.3. carrier-mute threshold the carrier-mute threshold has been made program- mable according to the user ? s preferences. an internal hysteresis ensures stable behavior. table 6 ? 7: write register on i 2 c subaddress 10 hex : a2 threshold register address function name thresholds 00 22 hex (write) a2 threshold register defines threshold of all a2 and eia_j standards for stereo and bilingual detection bit[15:0] 07f0 hex force mono identification ... 0190 hex default setting after reset ... 00a0 hex minimum threshold for stable detection recommended range : 00a0 hex ...03c0 hex a2_thresh table 6 ? 8: write register on i 2 c subaddress 10 hex : carrier-mute threshold register address function name thresholds 00 24 hex (write) carrier-mute threshold register defines threshold for the carrier mute feature bit[15:0] 0000 hex carrier-mute always on (both channels muted) ... 002a hex default setting after reset ... 07ff hex carrier-mute always off (both channels forced on) recommended range : 0014 hex ...0050 hex cm_thresh msp 34x5g preliminary data sheet 82 micronas 6.3.4. register ad_cv the use of this register is no longer recommended. use it only in cases where compatibility to the msp 34x5d is required. using the standard selection register together with the modus regis- ter provides a more economic way to program the msp 34x5g note: this register is initialized during standard selection and is automatically updated when automatic sound select (modus[0]=1) is on. table 6 ? 9: ad_cv register; reset status: all bits are ? 0 ? ad_cv (00 bb hex ) automatic setting by standard select register bit function settings 2-8, 0a-51 hex 9 [0] not used must be set to 0 0 0 [1 : 6] reference level in case of automatic gain control = on (see table 6 ? 10). constant gain factor when automatic gain control = off (see table 6 ? 11). 101000 100011 [7] determination of automatic gain or constant gain 0 = constant gain 1 = automatic gain 11 [8] selection of sound if source (identical to modus[8]) 0 = ana_in1+ x x [9] msp-carrier-mute feature 0 = off: no mute 1 = on: mute as de- scribed in section 2.2.2. 11 [10 : 15] not used must be set to 0 0 0 x: not affected while choosing the tv sound standard by means of the standard select register table 6 ? 10: reference values for active agc (ad_cv[7] = 1) application input signal contains ad_cv [6:1] ref. value ad_cv [6:1] in decimal range of input signal at pin ana_in1+ terrestrial tv ? dual carrier fm ? nicam/fm ? nicam/am ? nicam only 2 fm carriers 1 fm and 1 nicam carrier 1 am and 1 nicam carrier 1 nicam carrier only 101000 101000 100011 010100 40 40 35 20 0.10 ? 3 v pp 1) 0.10 ? 3 v pp 1) 0.10 ? 1.4 v pp (recommended: 0.10 ? 0.8 v pp ) 0.05 ? 1.0 v pp sat 1 or more fm carriers 100011 35 0.10 ? 3 v pp 1) adr fm and adr carriers see drp 3510a data sheet 1) for signals above 1.4 vpp, the minimum gain of 3 db is switched, and overflow of the a/d converter may result. due to the robustness of the internal processing, the ic works up to and even more than 3 vpp, if norm conditions of fm/nicam or fm1/fm2 ratio are supposed. in this overflow case, a loss of fm-s/n-ratio of about 10 db may appear. preliminary data sheet msp 34x5g micronas 83 6.3.5. register mode_reg note: the use of this register is no longer recom- mended. it should be used only in cases where soft- ware compatibility to the msp 34x5d is required. using the standard selection register together with the modus register provides a more economic way to program the msp 34x5g. as soon as this register is applied, the msp 34x5g works in the msp 34x5d manual/compatibility mode . in this mode, btsc, eia-j, and fm-radio are disabled . only msp 34x5d features are available; the use of modus and status register is not allowed. the msp 34x5g is reset to the normal mode by first programming the modus register, followed by trans- mitting a valid standard code to the standard selection register. the register ? mode_reg ? contains the control bits determining the operation mode of the msp 34x5g in the msp 34x5d manual/compatibility mode; table 6 ? 12 explains all bit positions. table 6 ? 11: ad_cv parameters for constant input gain (ad_cv[7]=0) step ad_cv [6:1] constant gain gain input level at pin ana_in1+ and ana_in2+ 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 000000 000001 000010 000011 000100 000101 000110 000111 001000 001001 001010 001011 001100 001101 001110 001111 010000 010001 010010 010011 010100 3.00 db 3.85 db 4.70 db 5.55 db 6.40 db 7.25 db 8.10 db 8.95 db 9.80 db 10.65 db 11.50 db 12.35 db 13.20 db 14.05 db 14.90 db 15.75 db 16.60 db 17.45 db 18.30 db 19.15 db 20.00 db maximum input level: 3 v pp (fm) or 1 v pp (nicam) 1) maximum input level: 0.14 v pp 1) for signals above 1.4 vpp, the minimum gain of 3 db is switched, and overflow of the a/d converter may result. due to the robustness of the internal processing, the ic works up to and even more than 3 vpp, if norm conditions of fm/nicam or fm1/fm2 ratio are supposed. in this overflow case, a loss of fm-s/n-ratio of about 10 db may appear. msp 34x5g preliminary data sheet 84 micronas table 6 ? 12: control word ? mode_reg ? ; reset status: all bits are ? 0 ? mode_reg 00 83 hex automatic setting by standard select register bit function comment definition 2 - 5 8,a,b 9 [0] not used 0 : must be used 0 0 0 [1] dctr_tri digital control out 0/1 tri-state 0 : active 1 : tri-state xxx [2] i 2 s_tri i 2 s outputs tri-state (i2s_cl, i2s_ws, i2s_da_out) 0 : active 1 : tri-state xxx [3] i 2 s mode 1) master/slave mode of the i 2 s bus 0 : master 1 : slave xxx [4] i 2 s_ws mode ws due to the sony or philips-format 0 : sony 1 : philips xxx [5] not used 1 : recommended x x x [6] nicam 1) mode of msp-ch1 0 : fm 1 : nicam 011 [7] not used 0 : must be used 0 0 0 [8] fm am mode of msp-ch2 0 : fm 1 : am 001 [9] hdev high deviation mode (channel matrix must be sound a) 0 : normal 1 : high deviation mode 000 [11:10] not used 0 : must be used 0 0 0 [12] msp-ch1 gain see also table 6 ? 14 0 : gain = 6 db 1 : gain = 0 db 000 [13] fir1-filter coeff. set see also table 6 ? 14 0 : use fir1 1 : use fir2 100 [14] adr mode of msp-ch1/ adr-interface 0 : normal mode/tri-state 1 : adr-mode/active 000 [15] am-gain gain for am demodulation 0 : 0 db (default. of mspb) 1 : 12 db (recommended) 111 1) nicam and i 2 s-master mode are not allowed simultaneously x: not affected by standard select register preliminary data sheet msp 34x5g micronas 85 6.3.6. fir-parameter, registers fir1 and fir2 note: the use of this register is no longer recom- mended. use it only in cases where software compati- bility to the msp 34x5d is required. using the stan- dard selection register together with the modus register provides a more economic way to program the msp 34x5g. data shaping and/or fm/am bandwidth limitation is performed by a pair of linear phase finite impulse response filters (fir-filter). the filter coefficients are programmable and either are configured automatically by the standard select register or written manu- ally by the control processor via the control bus. two not necessarily different sets of coefficients are required: one for msp-ch1 (nicam or fm2) and one for msp-ch2 (fm1 = fm-mono). in table 6 ? 14 several coefficient sets are proposed. to load the fir-filters, the following data values are to be transferred 8 bits at a time embedded lsb-bound in a 16-bit word . the loading sequences must be obeyed. to change a coefficient set, the complete block fir1 or fir2 must be transmitted. note: for compatibility with msp 3415b, imreg1 and imreg2 have to be transmitted. the value for imreg1 and imreg2 is 004. due to the partitioning to 8-bit units, the values 04 hex , 40 hex , and 00 hex arise. 6.3.7. dco-registers note: the use of this register is no longer recom- mended. it should be used only in cases where soft- ware compatibility to the msp 34x5d is required. using the standard selection register together with the modus register provides a more economic way to program the msp 34x5g. when selecting a tv-sound standard by means of the standard select register, all frequency tuning is performed automatically. if manual setting of the tuning frequency is required, a set of 24-bit registers determining the mixing frequen- cies of the quadrature mixers can be written manually into the ic. in table 6 ? 15, some examples of dco reg- isters are listed. it is necessary to divide them up into low part and high part. the formula for the calculation of the registers for any chosen if-frequency is as fol- lows: incr dec = int(f/fs ? 2 24 ) with: int = integer function f = if-frequency in mhz f s = sampling frequency (18.432 mhz) conversion of incr into hex-format and separation of the 12-bit low and high parts lead to the required regis- ter values (dco1_hi or _lo for msp-ch1, dco2_hi or lo for msp-ch2). table 6 ? 13: loading sequence for fir-coefficients fir1 00 01 hex (msp-ch1: nicam/fm2) no. symbol name bits value 1 nicam/fm2_coeff. (5) 8 see table 6 ? 14 2 nicam/fm2_coeff. (4) 8 3 nicam/fm2_coeff. (3) 8 4 nicam/fm2_coeff. (2) 8 5 nicam/fm2_coeff. (1) 8 6 nicam/fm2_coeff. (0) 8 fir2 00 05 hex (msp-ch2: fm1/am) no. symbol name bits value 1imreg1 8 04 hex 2 imreg1 / imreg2 8 40 hex 3imreg2 8 00 hex 4 fm/am_coef (5) 8 see table 6 ? 14 5 fm/am_coef (4) 8 6 fm/am_coef (3) 8 7 fm/am_coef (2) 8 8 fm/am_coef (1) 8 9 fm/am_coef (0) 8 msp 34x5g preliminary data sheet 86 micronas table 6 ? 14: 8-bit fir-coefficients (decimal integer) for msp 34x0d; reset status: all coefficients are ? 0 ? coefficients for fir1 00 01 hex and fir2 00 05 hex terrestrial tv standards b/g-, d/k- nicam-fm i- nicam-fm l- nicam-am b/g-, d/k-, m-dual fm 130 khz 180 khz 200 khz 280 khz 380 khz 500 khz auto- search coef(i) fir1 fir2 fir1 fir2 fir1 fir2 fir2 fir2 fir2 fir2 fir2 fir2 fir2 fir2 0 ? 2323 ? 2 ? 4 3 7393 ? 8 ? 1 ? 1 ? 1 1 ? 818 418 ? 8 ? 12 18 53 18 18 ? 8 ? 9 ? 1 ? 1 2 ? 10 27 ? 627 ? 10 ? 9 27 642827 4 ? 16 ? 8 ? 8 3 10 48 ? 4 48 10 23 48 119 47 48 36 5 2 2 4 50 66 40 66 50 79 66 101 55 66 78 65 59 59 5 86 72 94 72 86 126 72 127 64 72 107 123 126 126 mode- reg[12] 0 0 0 0 111111 0 mode- reg[13] 0 0 0 1 111111 0 for compatibility, except for the fir2-am and the autosearch-sets, the fir-filter programming as used for the msp 3415b is also possible. table 6 ? 15: dco registers for the msp 34x5g; reset status: dco_hi/lo = ? 0000 ? dco1_lo 00 93 hex , dco1_hi 00 9b hex ; dco2_lo 00 a3 hex , dco2_hi 00 ab hex freq. mhz dco_hi/hex dco_lo/hex freq. mhz dco_hi/hex dco_lo/hex 4.5 03e8 000 5.04 5.5 5.58 5.7421875 0460 04c6 04d8 04fc 0000 038e 0000 00aa 5.76 5.85 5.94 0500 0514 0528 0000 0000 0000 6.0 6.2 6.5 6.552 0535 0561 05a4 05b0 0555 0c71 071c 0000 6.6 6.65 6.8 05ba 05c5 05e7 0aaa 0c71 01c7 7.02 0618 0000 7.2 0640 0000 7.38 0668 0000 7.56 0690 0000 b fm - satellite fir filter corresponds to a band-pass with a band- width of b = 130 to 500 khz f c frequency preliminary data sheet msp 34x5g micronas 87 6.4. manual/compatibility mode: description of demodulator read registers note: the use of these register is no longer recom- mended. it should be used only in cases where soft- ware compatibility to the msp 34x5d is required. using the standard selection register together with the status register provides a more economic way to program the msp 34x5g and to retrieve infor- mation from the ic. all registers except c_ad_bits are 8 bit wide. they can be read out of the ram of the msp 34x5g if the msp 34x5d compatibility mode is required. all transmissions take place in 16-bit words. the valid 8-bit data are the 8 lsbs of the received data word. if the automatic sound select feature is not used, the nicam or fm-identification parameters must be read and evaluated by the controller in order to enable appropriate switching of the channel select matrix of the baseband processing part. the fm-identification registers are described in section 6.6.1. to handle the nicam-sound and to observe the nicam-quality, at least the registers c_ad_bits and error_rate must be read and evaluated by the controller. addi- tional data bits and cib bits, if supplied by the nicam transmitter, can be obtained by reading the registers add_bits and cib_bits. 6.4.1. nicam mode control/additional data bits register nicam operation mode control bits and a[2:0] of the additional data bits. format: important: ? s ? = bit[0] indicates correct nicam-syn- chronization (s = 1). if s = 0, the msp 3415/3455g has not yet synchronized correctly to frame and sequence, or has lost synchronization. the remaining read registers are therefore not valid. the msp mutes the nicam output automatically and tries to synchro- nize again as long as mode_reg[6] is set. the operation mode is coded by c4-c1 as shown in ta b l e 6 ? 16. note: it is no longer necessary to read out and evalu- ate the c_ad_bits. all evaluation is performed in the msp and indicated in the status register. 6.4.2. additional data bits register contains the remaining 8 of the 11 additional data bits. the additional data bits are not yet defined by the nicam 728 system. format: 6.4.3. cib bits register cib bits 1 and 2 (see nicam 728 specifications). format: msb c_ad_bits 00 23 hex lsb 11...76543210 auto _fm ... a[2] a[1] a[0] c4 c3 c2 c1 s table 6 ? 16: nicam operation modes as defined by the ebu nicam 728 specification c4 c3 c2 c1 operation mode 0 0 0 0 stereo sound (nicama/b), independent mono sound (fm1) 0 0 0 1 two independent mono signals (nicama, fm1) 0 0 1 0 three independent mono channels (nicama, nicamb, fm1) 0 0 1 1 data transmission only; no audio 1 0 0 0 stereo sound (nicama/b), fm1 carries same channel 1 0 0 1 one mono signal (nicama). fm1 carries same channel as nicama 1 0 1 0 two independent mono channels (nicama, nicamb). fm1 carries same channel as nicama 1 0 1 1 data transmission only; no audio x 1 x x unimplemented sound coding option (not yet defined by ebu nicam 728 specification) auto_fm: monitor bit for the auto_fm status: 0: nicam source is nicam 1: nicam source is fm msb add_bits 00 38 hex lsb 76543210 a[10] a[9] a[8] a[7] a[6] a[5] a[4] a[3] msb cib_bits 00 3e hex lsb 76543210 xxxxxxcib1cib2 msp 34x5g preliminary data sheet 88 micronas 6.4.4. nicam error rate register average error rate of the nicam reception in a time interval of 182 ms, which should be close to 0. the ini- tial and maximum value of error_rate is 2047. this value is also active if the nicam bit of mode_reg is not set. since the value is achieved by filtering, a certain transition time (approx. 0.5 sec) is unavoidable. acceptable audio may have error rates up to a value of 700 int. individual evaluation of this value by the controller and an appropriate threshold may define the fallback mode from nicam to fm/ am-mono in case of poor nicam reception. the bit error rate per second (ber) can be calculated by means of the following formula: ber= error_rate * 12.3*10 ? 6 /s 6.4.5. pll_caps readback register it is possible to read out the actual setting of the pll_caps. in standard applications, this register is not of interest for the customer. 6.4.6. agc_gain readback register it is possible to read out the actual setting of agc_gain in automatic gain mode. in standard applications, this register is not of interest for the cus- tomer . 6.4.7. automatic search function for fm-carrier detection in satellite mode the am demodulation ability of the msp 3415g and msp 3455g offers the possibility to calculate the ? field strength ? of the momentarily selected fm carrier, which can be read out by the controller. in sat receiv- ers, this feature can be used to make automatic fm carrier search possible. for this, the msp has to be switched to am-mode (mode_reg[8]), fm-prescale must be set to 7f hex =+127 dec , and the fm dc notch (see section 6.5.7.) must be switched off. the sound-if fre- quency range must now be ? scanned ? in the msp-channel 2 by means of the programmable quadrature mixer with an appropriate incremental fre- quency (i.e. 10 khz). after each incrementation, a field strength value is available at the quasi-peak detector output (quasi-peak detector source must be set to fm), which must be examined for relative maxima by the controller. this results in either continuing search or switching the msp back to fm demodulation mode. during the search process, the fir2 must be loaded with the coefficient set ? autosearch ? , which enables small bandwidth, resulting in appropriate field strength characteristics. the absolute field strength value (can be read out of ? quasi peak detector output fm1 ? ) also gives information on whether a main fm carrier or a subcarrier was detected; and as a practical consequence, the fm bandwidth (fir1/2) and the deemphasis (50 s or adaptive) can be switched accordingly. due to the fact that a constant demodulation frequency offset of a few khz, leads to a dc level in the demodu- lated signal, further fine tuning of the found carrier can be achieved by evaluating the ? dc level readout fm1 ? . therefore, the fm dc notch must be switched on, and the demodulator part must be switched back to fm-demodulation mode. for a detailed description of the automatic search function, please refer to the corresponding msp win- dows software. error_rate 00 57 hex error free 0000 hex maximum error rate 07ff hex pll_caps 02 1f hex l minimum frequency 1111 1111 ff hex nominal frequency 0101 0110 56 hex reset maximum frequency 0000 0000 00 hex pll_caps 02 1f hex h pll open xxxx xxx0 pll closed xxxx xxx1 agc_gain 02 1e hex max. amplification (20 db) 0001 0100 14 hex min. amplification (3 db) 0000 0000 00 hex preliminary data sheet msp 34x5g micronas 89 6.5. manual/compatibility mode: description of dsp write registers 6.5.1. additional channel matrix modes this table shows more modes for the channel matrix registers. the sum/difference mode can be used together with the quasi-peak detector to determine the sound mate- rial mode. if the difference signal on channel b (right) is near to zero, and the sum signal on channel a (left) is high, the incoming audio signal is mono. if there is a significant level on the difference signal, the incoming audio is stereo. 6.5.2. volume modes of scart1 output 6.5.3. fm fixed deemphasis note: this register is initialized during standard selection and is automatically updated when auto- matic sound select (modus[0]=1) is on. 6.5.4. fm adaptive deemphasis note: this register is initialized during standard selection and is automatically updated when auto- matic sound select (modus[0]=1) is on. 6.5.5. nicam deemphasis a j17 deemphasis is always applied to the nicam sig- nal. it is not switchable. loudspeaker matrix 00 08 hex l scart1 matrix 00 0a hex l i 2 s matrix 00 0b hex l quasi-peak detector matrix 00 0c hex l sum/diff 0100 0000 40 hex ab_xchange 0101 0000 50 hex phase_change_b 0110 0000 60 hex phase_change_a 0111 0000 70 hex a_only 1000 0000 80 hex b_only 1001 0000 90 hex volume mode scart1 00 07 hex [3:0] linear 0000 0 hex reset logarithmic 0001 1 hex linear mode volume scart1 00 07 hex h off 0000 0000 00 hex reset 0 db gain (digital full scale (fs) to 2 v rms output) 0100 0000 40 hex +6 db gain ( ? 6 dbfs to 2 v rms output) 0111 1111 7f hex fm deemphasis 00 0f hex h 50 s 0000 0000 00 hex reset 75 s 0000 0001 01 hex j17 0000 0100 04 hex off 0011 1111 3f hex fm adaptive deemphasis wp1 00 0f hex l off 0000 0000 00 hex reset wp1 0011 1111 3f hex msp 34x5g preliminary data sheet 90 micronas 6.5.6. identification mode for a2 stereo systems to shorten the response time of the identification algo- rithm after a program change between two fm-stereo capable programs, the reset of the ident-filter can be applied. sequence: 1. program change 2. reset ident-filter 3. set identification mode back to standard b/g or m 4. wait approx. 500 ms 5. read stereo detection register note: this register is initialized during standard selection and is automatically updated when auto- matic sound select (modus[0]=1) is on. 6.5.7. fm dc notch the dc compensation filter (fm dc notch) for fm input can be switched off. this is used to speed up the automatic search function (see section 6.4.7.). in nor- mal fm-mode, the fm dc notch should be switched on. 6.6. manual/compatibility mode: description of dsp read registers all readable registers are 16-bit wide. transmissions via i 2 c bus have to take place in 16-bit words. some of the defined 16-bit words are divided into low and high byte, thus holding two different control entities. these registers are not writable. 6.6.1. stereo detection register for a2 stereo systems note: it is no longer necessary to read out and evalu- ate the a2 identification level. all evaluation is per- formed in the msp and indicated in the status regis- ter. 6.6.2. dc level register the dc level register measures the dc component of the incoming fm signals (fm1 and fm2). this can be used for seek functions in satellite receivers and for if fm frequencies fine tuning. a too low demodulation frequency (dco) results in a positive dc-level and vice versa. for further processing, the dc content of the demodulated fm signals is suppressed. the time constant , defining the transition time of the dc level register, is approximately 28 ms. identification mode 00 15 hex l standard b/g (german stereo) 0000 0000 00 hex reset standard m (korean stereo) 0000 0001 01 hex reset of ident-filter 0011 1111 3f hex fm dc notch 00 17 hex l on 0000 0000 00 hex reset off 0011 1111 3f hex stereo detection register 00 18 hex h stereo mode reading (two ? s complement) mono near zero stereo positive value (ideal reception: 7f hex ) bilingual negative value (ideal reception: 80 hex) dc level readout fm1 (msp-ch2) 00 1b hex h+l dc level readout fm2 (msp-ch1) 00 1c hex h+l dc level [8000 hex ... 7fff hex ] values are 16 bit two ? s complement preliminary data sheet msp 34x5g micronas 91 6.7. demodulator source channels in manual mode 6.7.1. terrestric sound standards ta b l e 6 ? 17 shows the source channel assignment of the demodulated signals in case of manual mode for all terrestric sound standards. see table 2 ? 2 for the assignment in the automatic sound select mode. in manual mode for terrestric sound standards, only two demodulator sources are defined. 6.7.2. sat sound standards ta b l e 6 ? 18 shows the source channel assignment of the demodulated signals for sat sound standards. 6.8. exclusions of audio baseband features in general, all functions can be switched independently. two exceptions exist: 1. nicam cannot be processed simultaneously with the fm2 channel. 2. fm adaptive deemphasis cannot be processed simultaneously with fm-identification. 6.9. compatibility restrictions to msp 34x5d the msp 34x5g is fully hardware compatible to the msp 34x5d. however, to substitute a msp 34x5d by the corresponding msp 34x5g, the controller software has to be adapted slightly: 1. the register fm-matrix (00 0e hex low part) must be changed from ? no matrix (00 hex ) ? to ? sound a mono (03 hex ) ? during mono transmission of all tv-sound standards (see also table 6 ? 17). 2. with the msp 34x5g, the standard selection initializes the fm-deemphasis, which is not the case for the msp 34x5d. so, if standard selection is applied, this i 2 c instruction can be omitted. msp 34x5g preliminary data sheet 92 micronas table 6 ? 17: manual sound select mode for terrestric sound standards source channels of sound select block broadcasted sound standard selected msp standard code broadcasted sound mode fm matrix fm/am (use 0 for channel select) stereo or a/b (use 1 for channel select) b/g-fm d/k-fm m-korea m-japan 03 04, 05 02 30 mono sound a mono mono mono stereo german stereo korean stereo stereo stereo bilingual, languages a and b no matrix left = a right = b left = a right = b b/g-nicam l-nicam i-nicam d/k-nicam d/k-nicam (with high deviation fm) 08 09 0a 0b 0c 0d nicam not available or nicam error rate too high sound a mono 1) analog mono no sound with auto_fm: analog mono mono sound a mono 1) analog mono nicam mono stereo sound a mono 1) analog mono nicam stereo bilingual, languages a and b sound a mono 1) analog mono left = nicam a right = nicam b btsc 20 mono sound a mono mono mono stereo korean stereo stereo stereo mono + sap sound a mono mono mono stereo + sap korean stereo stereo stereo 21 mono sound a mono mono mono stereo mono + sap no matrix left = mono right = sap left = mono right = sap stereo + sap fm-radio 40 mono sound a mono mono mono stereo korean stereo stereo stereo 1) automatic refresh to sound a mono, do not write any other value to the register fm matrix! table 6 ? 18: manual sound select modes for sat-standards source channels of sound select block for sat-modes broadcasted sound standard selected msp standard code broadcasted sound mode fm matrix fm/am (source select: 0) stereo or a/b (source select: 1) stereo or a (source select: 3) stereo or b (source select: 4) fm sat 6, 50 hex mono sound a mono mono mono mono mono 51 hex stereo no matrix stereo stereo stereo stereo bilingual no matrix left = a (fm1) right = b (fm2) left = a (fm1) right = b (fm2) a (fm1) b (fm2) preliminary data sheet msp 34x5g micronas 93 7. appendix d: application information 7.1. phase relationship of analog outputs the user does not need to correct output phases when using the loudspeaker output directly. the scart1 output has opposite phase. the following schematics shows the phase relation- ship of all analog inputs and outputs. fig. 7 ? 1: phase diagram of the msp 34x5g scart1 scart1 scart2 mono loudspeaker scart1-ch. mono, scart1...2 scart dsp input select scart output select audio baseband processing msp 34x5g preliminary data sheet 94 micronas 7.2. application circuit sc1_out_l sc1_out_r ahvsup ahvss avsup dvsup dvss avss vref1 vref2 5 v 5 v 8 v avss 5v 5v capl_m vreftop agndc ana_in1+ ana_in ? xtal_in xtal_out msp 34x5g d_ctr_i/o_0 d_ctr_i/o_1 testen 100 ? 100 ? 22 f 22 f + + 1 nf 1 nf dacm_r dacm_l 1 f 1 f loudspeaker tuner signal gnd sif 1 in 56 pf 56 pf + 3.3 f 100 nf 100 nf 10 f + - 8v (5v) 18.432 mhz + 10 f mono_in sc1_in_l sc1_in_r asg sc2_in_l sc2_in_r standbyq adr_sel i2c_da i2c_cl 220 pf alternative circuit for sif-input for more attenuation of video 100 p 56 p 1k ? ana_in1+ ahvss 330 nf 330 nf 330 nf 330 nf 330 nf dvss dvss ahvss components: c s. section 4.6.2. resetq (from controller, see section 4.6.3.3.) 1.5 nf 470 pf 10 f 1.5 nf 470 pf 10 f 1.5 nf 470 pf 10 f adr_ws adr_cl adr_da i2s_ws i2s_cl i2s_da_in1 i2s_da_in2 i2s_da_out (5 v) ahvss ahvss ahvss resetq preliminary data sheet msp 34x5g micronas 95 all information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. any new issue of this data sheet invalidates previous issues. product availability and delivery are exclusively subject to our respective order confirmation form; the same applies to orders based on development samples deliv- ered. by this publication, micronas gmbh does not assume responsibil- ity for patent infringements or other rights of third parties which may result from its use. further, micronas gmbh reserves the right to revise this publication and to make changes to its content, at any time, without obligation to notify any person or entity of such revisions or changes. no part of this publication may be reproduced, photocopied, stored on a retrieval system, or transmitted without the express written consent of micronas gmbh. msp 34x5g preliminary data sheet 96 micronas micronas gmbh hans-bunte-strasse 19 d-79108 freiburg (germany) p.o. box 840 d-79008 freiburg (germany) tel. +49-761-517-0 fax +49-761-517-2174 e-mail: docservice@micronas.com internet: www.micronas.com printed in germany order no. 6251-480-3pd 8. appendix e: msp 34x5g version history msp 3435g-a2 first release for btsc-stereo/sap and fm-radio. msp 34x5g-b5 ? additional package plqfp64 ? digital input specification changed as of version b5 and later (see section 4.6. on page 53) ? max. analog high supply voltage ahvsup 8.7 v. ? supply currents changed as of version b5 and later (see section 4.6.3. on page 58) ? programmable a2 and carrier mute thresholds ? new d/k standard 0d hex : hdev3 and nicam ? additional preference in automatic standard detec- tion msp 34x5g-b6 ? improved am-performance (see page 69) ? new d/k standard for poland (see table 3 ? 7 on page 20) ? improved i 2 c hardware problem handling (see section 3.1.1. on page 15) ? faster system-d/k-loop for stereo detection ? extended features in the control register (see section 3.1.2. on page 16) msp 34x5g-b8 ? fine-tuning of a2-identification and carrier mute ? eia-j identification: faster transition time stereo/ bilingual to mono ? j17 fm-deemphasis implemented ? input specification for resetq and testen changed 9. data sheet history 1. preliminary data sheet: ? msp 34x5g multistandard sound processor family, edition oct. 26, 1998, 6251- 480-1pd. first release of the preliminary data sheet. 2. preliminary data sheet: ? msp 34x5g multistandard sound processor family ? , edition july 11, 2000, 6251- 480-2pd. second release of the preliminary data sheet. major changes: ? section specifications: specification for plqfp64 package added ? specification for version b5 and b6 added (see appendix e: version history) ? reset description modified ? i 2 s and adr functionality added ? msp 3425g and msp 3465g added ? multistandard controller software flow diagram added 3. preliminary data sheet: ? msp 34x5g multistandard sound processor family ? , march 5, 2001, 6251-480- 3pd. third release of the preliminary data sheet. major changes: ? section 4.2.: pin allocation for plqfp64 corrected ? i 2 c-bus description changed ? acb register: documentation for bit allocation d_ctr_i/o changed micronas 97 micronas page 1 of 1 subject: data sheet concerned: supplement: edition: preliminary data sheet supplement version changes within the msp 34xxg family: for a detailed description of the below-mentioned items, see the corresponding data sheets. for quick reference, check the version history in the data sheet appendices. msp 34x0g a4 b4 b5 b6 b8 msp 34x1g a1 a2 b8 msp 34x2g a1 msp 34x5g a4 b5 b6 b8 msp 34x7g b6 b8 technology 0.8 0.5 0.5 0.5 0.45 power dissipation (typical) at 8 v operation msp 34x0/x1/x5/x7 msp 34x2 740 mw 640 mw 640 mw 640 mw 690 mw 600 mw digital input specification change x x x specification of max. analog high voltage (ahvsup) 8.4 v 8.4 v 8.7 v 8.7 v 8.7 v programmable a2 and carrier mute thresholds x x x new standard select mode 0d hex : d/k-nicam together with hdev3 fm mode x x x additional preference color for 4.5 mhz carrier in automatic standard detection x x x improved am-performance (better snr and thd) x x new standard select mode 07 hex : d/k3 for poland x x faster system d/k loop for stereo detection (standards 4, 5, 7, b with ass = on) x x improved i 2 c hardware problem handling x x extended features in the control register (readout hardware / reset status) x x micronas dynamic bass (mdb) msp 34x0/x1/x2 x x micronas dynamic bass (improved mdb) msp 34x0/x1/x2 x faster identification for all standards, major speedup of identification for eia-j standard x faster carrier mute x j17 deemphasis x msp 34xxg version history all msp 34xxg data sheets no. 2/ 6251-525-2pds oct. 11, 2000 msp 34xxg |
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